-Fixed fast accumulator model;
-Generated proper HEX files to match 48-vis rewiring stage;
-Stripped development code from top level;
-Added FIXME tags to top level with descriptions;
-Added recorded .rec files;
-Set coefficient width back to 18b;
-Set WPFB output to 9b so correlator output becomes a nice 32b;
-Verified in sim: PLOTs are slightly off!

- Switched fail and ok in reg map
- Removed comments  

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

 readout. As the MSbit was missing, usedw would wrap from 127 to 0 (instead
 of indicating 128) which caused the FIFO to no longer be read out and
 overflowing under cetain circumstances (gaps in the data = no valid signal
 to trigger FIFO readout while the adder+fifo registers still output 4
 valid words after fifo src_in.ready goining down).

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more clearly distinghuis it from ctrl_drv_mosi for the IO driver side.