Replaced port types

libraries/io/ddr3/src/vhdl/ddr3.vhd

@@ -24,13 +24,14 @@
 LIBRARY ip_stratixiv_ddr3_uphy_4g_800_master_lib;
 LIBRARY ip_stratixiv_ddr3_uphy_4g_800_slave_lib;
 
-LIBRARY IEEE, common_lib, dp_lib;
+LIBRARY IEEE, common_lib, dp_lib, tech_ddr_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL; 
 USE common_lib.common_mem_pkg.ALL;
-USE work.ddr3_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.ddr3_pkg.ALL;
 
 ENTITY ddr3 IS
   GENERIC(
@@ -99,9 +100,9 @@ ENTITY ddr3 IS
     ser_term_ctrl_in   : IN    STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
     par_term_ctrl_in   : IN    STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
 
-    phy_in             : IN    t_ddr3_phy_in;
-    phy_io             : INOUT t_ddr3_phy_io;
-    phy_ou             : OUT   t_ddr3_phy_ou
+    phy_in             : IN    t_tech_ddr3_phy_in;
+    phy_io             : INOUT t_tech_ddr3_phy_io;
+    phy_ou             : OUT   t_tech_ddr3_phy_ou
    );
 END ddr3;