-Cleaned code, added a note.

libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd

@@ -136,9 +136,9 @@ BEGIN
         g_data_w         => 2*c_acc_data_w,
         g_use_ctrl       => FALSE,
         g_use_complex    => TRUE,
-        g_fifo_size      => g_nof_accumulators,
-        g_fifo_af_margin => 1
-      )
+        g_fifo_size      => g_nof_accumulators, --Note: Even though we start reading the FIFO at g_nof_accumulators-c_adder_latency-c_fifo_latency-1 words,
+        g_fifo_af_margin => 1                   --we still need g_nof_accumulators of capacity as 3 cycles of valid data is stored in the reg_snk_in and adder registers.
+      )                                         --These 3 words may fill the FIFO while it is not being read out (in case of gaps in the input data).
       PORT MAP (
         rst         => rst,
         clk         => clk,
@@ -172,8 +172,6 @@ BEGIN
       nxt_dp_block_gen_snk_in_arr(i).im <= RESIZE_DP_DSP_DATA(dp_fifo_sc_src_out_arr(i).im);
       
       nxt_dp_block_gen_snk_in_arr(i).valid <= '1' WHEN TO_UINT(acc_cnt_arr(i))<g_nof_accumulators   AND dp_fifo_sc_src_out_arr(i).valid='1' ELSE '0';
---      nxt_dp_block_gen_snk_in_arr(i).sop   <= '1' WHEN TO_UINT(acc_cnt)=0                    AND dp_fifo_sc_src_out_arr(0).valid='1' ELSE '0';
---      nxt_dp_block_gen_snk_in_arr(i).eop   <= '1' WHEN TO_UINT(acc_cnt)=g_nof_accumulators-1 AND dp_fifo_sc_src_out_arr(0).valid='1' ELSE '0';
     END GENERATE;  
 
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