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Commit d51f8638 authored by Eric Kooistra's avatar Eric Kooistra
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Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... 

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.
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libraries/io/ddr/hdllib.cfg
+ 4
− 4
View file @ d51f8638
......@@ -24,11 +24,11 @@ test_bench_files =
modelsim_search_libraries =
# stratixiv only
# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
# altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
# arria10 only
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
# altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
# both (will yield errors if the technology library is not available in simulator but these errors can be ignored)
# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
# altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
......
libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+ 10
− 14
View file @ d51f8638
......@@ -48,8 +48,7 @@ ENTITY tb_io_ddr IS
g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
g_use_ddr_memory_model : BOOLEAN := FALSE; -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
g_cross_domain_dvr_ctlr : BOOLEAN := FALSE; -- when TRUE insert clock cross domain logic
g_cross_domain_dvr_ctlr : BOOLEAN := TRUE; -- when TRUE insert clock cross domain logic
g_ctlr_ref_clk_period : TIME := 5000 ps; -- 200 MHz
g_dvr_clk_period : TIME := 5000 ps; -- 50 MHz
g_dp_clk_period : TIME := 5000 ps; -- 200 MHz
......@@ -399,7 +398,6 @@ BEGIN
GENERIC MAP(
g_technology => g_technology,
g_tech_ddr => c_tech_ddr,
g_use_ddr_memory_model => g_use_ddr_memory_model, -- when TRUE use internal DDR memory model
g_cross_domain_dvr_ctlr => c_cross_domain_dvr_ctlr,
g_cross_domain_delay_len => c_meta_delay_len,
g_wr_data_w => c_dp_data_w,
......@@ -461,17 +459,15 @@ BEGIN
phy_in => phy_in
);
external_ddr_memory_model : IF g_use_ddr_memory_model=FALSE GENERATE
u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
GENERIC MAP (
g_sim => TRUE,
g_tech_ddr => c_tech_ddr
)
PORT MAP (
mem_in => phy_ou,
mem_io => phy_io
);
END GENERATE;
u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
GENERIC MAP (
g_sim => TRUE,
g_tech_ddr => c_tech_ddr
)
PORT MAP (
mem_in => phy_ou,
mem_io => phy_io
);
END ARCHITECTURE str;
......
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+ 18
− 19
View file @ d51f8638
......@@ -52,7 +52,6 @@ BEGIN
-- g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-- g_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_use_ddr_memory_model : BOOLEAN := TRUE; -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
-- g_cross_domain_dvr_ctlr : BOOLEAN := FALSE; -- when TRUE insert clock cross domain logic
-- g_ctlr_ref_clk_period : TIME := 5 ns; -- 200 MHz
-- g_dvr_clk_period : TIME := 5 ns; -- 50 ns
......@@ -68,28 +67,28 @@ BEGIN
-- g_wr_flush_mode : STRING := "SYN" -- "VAL", "SOP", "SYN"
gen_ddr3 : IF c_tech_ddr.name="DDR3" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(2));
u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(3));
u_ext_memory_model : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(4));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 8,8192, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(5));
u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(6));
u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(7));
u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8));
u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9));
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(10));
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(11));
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_fill_wrfifo_on_next_valid : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 1, 4, 2, "VAL") PORT MAP (tb_end_vec(1));
u_fill_wrfifo_on_next_sop : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 3, 4, 2, "SOP") PORT MAP (tb_end_vec(2));
u_fill_wrfifo_on_next_sync : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 1, 256, 1000, 2, 4, 1, 2, "SYN") PORT MAP (tb_end_vec(3));
u_cross_domain : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, 5 ns, 5 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(4));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 8,8192, 2500, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(5));
u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(6));
u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(7));
u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8));
u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 8 ns, 1,8192, 2500, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(9));
u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(10));
u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 256, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(11));
END GENERATE;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
gen_ddr4 : IF c_tech_ddr.name="DDR4" GENERATE
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
u_default : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8 ns, 4, 512, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
END GENERATE;
p_tb_end : PROCESS
......
libraries/technology/ddr/tech_ddr.vhd
+ 3
− 28
View file @ d51f8638
......@@ -24,11 +24,6 @@
-- Description:
-- The component also supports different types of DDR, so DDR3 and DDR4.
-- Remark:
-- In simulation use g_use_ddr_memory_model=TRUE to also include the DDR
-- memory model that is internally available within tech_ddr. This avoids
-- having to connect a DDR memory model at top level in the test bench.
-- Default g_use_ddr_memory_model must be FALSE to avoid further analysis
-- of the DDR memory model component by synthesis.
LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
......@@ -40,8 +35,7 @@ USE work.tech_ddr_pkg.ALL;
ENTITY tech_ddr IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_tech_ddr : t_c_tech_ddr;
g_use_ddr_memory_model : BOOLEAN := FALSE
g_tech_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
......@@ -70,8 +64,6 @@ END tech_ddr;
ARCHITECTURE str OF tech_ddr IS
SIGNAL i_phy_ou : t_tech_ddr_phy_ou;
BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
......@@ -80,7 +72,7 @@ BEGIN
PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in,
phy_in, phy_io, i_phy_ou);
phy_in, phy_io, phy_ou);
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
......@@ -89,24 +81,7 @@ BEGIN
PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst,
ctlr_mosi, ctlr_miso,
phy_in, phy_io, i_phy_ou);
END GENERATE;
-- Include DDR memory model only for simulation
no_ddr_memory_model : IF g_use_ddr_memory_model=FALSE GENERATE
phy_ou <= i_phy_ou;
END GENERATE;
gen_ddr_memory_model: IF g_use_ddr_memory_model=TRUE GENERATE
u_tech_ddr_memory_model : ENTITY work.tech_ddr_memory_model
GENERIC MAP (
g_sim => g_use_ddr_memory_model,
g_tech_ddr => g_tech_ddr
)
PORT MAP (
mem_in => i_phy_ou,
mem_io => phy_io
);
phy_in, phy_io, phy_ou);
END GENERATE;
END str;
......
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