Added tech_ddr to librariues and copy statement for hex files

libraries/io/ddr3/hdllib.cfg

 hdl_lib_name = ddr3
 hdl_library_clause_name = ddr3_lib
-hdl_lib_uses_synth = common dp diag diagnostics ss 
+hdl_lib_uses_synth = common dp diag diagnostics ss tech_ddr 
 hdl_lib_uses_sim = 
 
 hdl_lib_technology =
@@ -20,7 +20,7 @@ synth_files =
     $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
     src/vhdl/ddr3.vhd
     src/vhdl/ddr3_transpose.vhd
-    $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3.vhd
+    src/vhdl/mms_ddr3.vhd
     $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3_capture.vhd
     $UNB/Firmware/modules/ddr3/src/vhdl/seq_ddr3.vhd
 
@@ -30,6 +30,11 @@ test_bench_files =
     tb/vhdl/tb_seq_ddr3.vhd
     tb/vhdl/tb_ddr3_transpose.vhd
 
+modelsim_copy_files =
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+
 modelsim_search_libraries =
 # stratixiv only
     altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver