-Fixed FIFO readout as it did not work properly with gapped data.

libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd

@@ -53,7 +53,7 @@ ARCHITECTURE str OF corr_accumulator IS
 
   -- Complex accumulator data width: wide enough to support g_integration_period accumulations
   CONSTANT c_acc_data_w               : NATURAL := g_data_w + ceil_log2(g_integration_period);
-  CONSTANT c_adder_latency            : NATURAL := 3;
+  CONSTANT c_adder_latency            : NATURAL := 2;
   CONSTANT c_fifo_latency             : NATURAL := 1;
 
   SIGNAL reg_snk_in_arr               :t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
@@ -148,7 +148,7 @@ BEGIN
   
       -- Shift out the first accumulated value when it aligns with the corresponding current value at the adder input
       -- . this produces the dp_fifo_sc_src_out_arr data in sync with reg_snk_in_arr data
-      dp_fifo_sc_src_in_arr(i).ready <= snk_in_arr(i).valid WHEN TO_UINT(dp_fifo_sc_usedw_arr(i))=g_nof_accumulators-c_adder_latency-c_fifo_latency ELSE '0';
+      dp_fifo_sc_src_in_arr(i).ready <= snk_in_arr(i).valid WHEN TO_UINT(dp_fifo_sc_usedw_arr(i))>=g_nof_accumulators-1-c_adder_latency-c_fifo_latency-1 ELSE '0';
   
     END GENERATE;