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Commit 8e1a6162 authored by Eric Kooistra's avatar Eric Kooistra
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Removed internal DDR memory model (now needs to be instantiated in tb). Use...

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.
parent 17ede428
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...@@ -51,13 +51,18 @@ ENTITY tech_ddr IS ...@@ -51,13 +51,18 @@ ENTITY tech_ddr IS
ctlr_mosi : IN t_mem_ctlr_mosi; ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_mem_ctlr_miso; ctlr_miso : OUT t_mem_ctlr_miso;
term_ctrl_out : OUT t_tech_ddr_phy_terminationcontrol; term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr_phy_terminationcontrol := c_tech_ddr_phy_terminationcontrol_rst; term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
-- PHY interface -- DDR3 PHY interface
phy_in : IN t_tech_ddr_phy_in; phy3_in : IN t_tech_ddr3_phy_in := c_tech_ddr3_phy_in_x;
phy_io : INOUT t_tech_ddr_phy_io; phy3_io : INOUT t_tech_ddr3_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou phy3_ou : OUT t_tech_ddr3_phy_ou;
-- DDR4 PHY interface
phy4_in : IN t_tech_ddr4_phy_in := c_tech_ddr4_phy_in_x;
phy4_io : INOUT t_tech_ddr4_phy_io;
phy4_ou : OUT t_tech_ddr4_phy_ou
); );
END tech_ddr; END tech_ddr;
...@@ -72,7 +77,7 @@ BEGIN ...@@ -72,7 +77,7 @@ BEGIN
PORT MAP (ref_clk, ref_rst, PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x, ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in, ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in,
phy_in, phy_io, phy_ou); phy3_in, phy3_io, phy3_ou);
END GENERATE; END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
...@@ -81,7 +86,7 @@ BEGIN ...@@ -81,7 +86,7 @@ BEGIN
PORT MAP (ref_clk, ref_rst, PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk, ctlr_gen_rst,
ctlr_mosi, ctlr_miso, ctlr_mosi, ctlr_miso,
phy_in, phy_io, phy_ou); phy4_in, phy4_io, phy4_ou);
END GENERATE; END GENERATE;
END str; END str;
......
...@@ -61,9 +61,9 @@ ENTITY tech_ddr_arria10 IS ...@@ -61,9 +61,9 @@ ENTITY tech_ddr_arria10 IS
ctlr_miso : OUT t_mem_ctlr_miso; ctlr_miso : OUT t_mem_ctlr_miso;
-- PHY interface -- PHY interface
phy_in : IN t_tech_ddr_phy_in; phy_in : IN t_tech_ddr4_phy_in;
phy_io : INOUT t_tech_ddr_phy_io; phy_io : INOUT t_tech_ddr4_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou phy_ou : OUT t_tech_ddr4_phy_ou
); );
END tech_ddr_arria10; END tech_ddr_arria10;
......
...@@ -20,8 +20,12 @@ ...@@ -20,8 +20,12 @@
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Purpose: DDR3 memory model for simulation. -- Purpose: DDR3 or DDR4 memory model for simulation.
-- Description: -- Description:
-- Dependent on g_tech_ddr.name either a DDR3 memory or a DDR4 memory model
-- gets instantiated.
-- If DDR3 is selected then the mem4 ports remain unused.
-- If DDR4 is selected then the mem3 ports remain unused.
-- The DDR3 memory model is not FPGA specific, but it was created by the example design for ip_stratixiv_ddr3_uphy_4g_800_master. -- The DDR3 memory model is not FPGA specific, but it was created by the example design for ip_stratixiv_ddr3_uphy_4g_800_master.
-- Therefore the ip_stratixiv_ddr3_uphy_4g_800_master_lib is needed if the model is used. -- Therefore the ip_stratixiv_ddr3_uphy_4g_800_master_lib is needed if the model is used.
...@@ -38,15 +42,17 @@ USE work.tech_ddr_mem_model_component_pkg.ALL; ...@@ -38,15 +42,17 @@ USE work.tech_ddr_mem_model_component_pkg.ALL;
ENTITY tech_ddr_memory_model IS ENTITY tech_ddr_memory_model IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := FALSE; -- Default FALSE: no DDR memory model instantiation, this also avoids further component evaluation by synthesis.
-- TRUE: instantiate DDR memory model for simulation;
g_tech_ddr : t_c_tech_ddr g_tech_ddr : t_c_tech_ddr
); );
PORT ( PORT (
-- PHY interface -- DDR3 PHY interface
mem_in : IN t_tech_ddr_phy_ou; mem3_in : IN t_tech_ddr3_phy_ou := c_tech_ddr3_phy_ou_x;
mem_io : INOUT t_tech_ddr_phy_io; mem3_io : INOUT t_tech_ddr3_phy_io;
mem_ou : OUT t_tech_ddr_phy_in mem3_ou : OUT t_tech_ddr3_phy_in;
-- DDR4 PHY interface
mem4_in : IN t_tech_ddr4_phy_ou := c_tech_ddr4_phy_ou_x;
mem4_io : INOUT t_tech_ddr4_phy_io;
mem4_ou : OUT t_tech_ddr4_phy_in
); );
END tech_ddr_memory_model; END tech_ddr_memory_model;
...@@ -60,7 +66,7 @@ ARCHITECTURE str OF tech_ddr_memory_model IS ...@@ -60,7 +66,7 @@ ARCHITECTURE str OF tech_ddr_memory_model IS
BEGIN BEGIN
gen_ip_stratixiv_ddr_memory_model : IF g_sim = TRUE AND g_tech_ddr.name="DDR3" GENERATE gen_ip_stratixiv_ddr_memory_model : IF g_tech_ddr.name="DDR3" GENERATE
u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
GENERIC MAP ( GENERIC MAP (
MEM_IF_CLK_EN_WIDTH => g_tech_ddr.cke_w, MEM_IF_CLK_EN_WIDTH => g_tech_ddr.cke_w,
...@@ -90,43 +96,43 @@ BEGIN ...@@ -90,43 +96,43 @@ BEGIN
MEM_VERBOSE => 1 MEM_VERBOSE => 1
) )
PORT MAP ( PORT MAP (
mem_a => mem_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- MEM_IF_ADDR_WIDTH mem_a => mem3_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- MEM_IF_ADDR_WIDTH
mem_ba => mem_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- MEM_IF_BANKADDR_WIDTH mem_ba => mem3_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- MEM_IF_BANKADDR_WIDTH
mem_ck => mem_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH mem_ck => mem3_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH
mem_ck_n => mem_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH mem_ck_n => mem3_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- MEM_IF_CK_WIDTH
mem_cke => mem_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- MEM_IF_CLK_EN_WIDTH mem_cke => mem3_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- MEM_IF_CLK_EN_WIDTH
mem_cs_n => mem_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- MEM_IF_CS_WIDTH mem_cs_n => mem3_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- MEM_IF_CS_WIDTH
mem_ras_n => slv(mem_in.ras_n), -- MEM_IF_CONTROL_WIDTH mem_ras_n => slv(mem3_in.ras_n), -- MEM_IF_CONTROL_WIDTH
mem_cas_n => slv(mem_in.cas_n), -- MEM_IF_CONTROL_WIDTH mem_cas_n => slv(mem3_in.cas_n), -- MEM_IF_CONTROL_WIDTH
mem_we_n => slv(mem_in.we_n), -- MEM_IF_CONTROL_WIDTH mem_we_n => slv(mem3_in.we_n), -- MEM_IF_CONTROL_WIDTH
mem_reset_n => mem_in.reset_n, mem_reset_n => mem3_in.reset_n,
mem_dm => mem_in.dm(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH mem_dm => mem3_in.dm(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH
mem_dq => mem_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- MEM_IF_DQ_WIDTH mem_dq => mem3_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- MEM_IF_DQ_WIDTH
mem_dqs => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH mem_dqs => mem3_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH
mem_dqs_n => mem_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH mem_dqs_n => mem3_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- MEM_IF_DQS_WIDTH
mem_odt => mem_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0) -- MEM_IF_ODT_WIDTH mem_odt => mem3_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0) -- MEM_IF_ODT_WIDTH
); );
END GENERATE; END GENERATE;
gen_ip_arria10_ddr_memory_model : IF g_sim = TRUE AND g_tech_ddr.name="DDR4" AND c_gigabytes=4 GENERATE gen_ip_arria10_ddr_memory_model : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 GENERATE
u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq
PORT MAP ( PORT MAP (
mem_ck => mem_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck mem_ck => mem4_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
mem_ck_n => mem_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n mem_ck_n => mem4_in.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_a => mem_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a mem_a => mem4_in.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
mem_act_n => slv(mem_in.act_n), -- .mem_act_n mem_act_n => slv(mem4_in.act_n), -- .mem_act_n
mem_ba => mem_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba mem_ba => mem4_in.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_bg => mem_in.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg mem_bg => mem4_in.bg(g_tech_ddr.bg_w-1 DOWNTO 0), -- .mem_bg
mem_cke => mem_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke mem_cke => mem4_in.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => mem_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n mem_cs_n => mem4_in.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_odt => mem_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt mem_odt => mem4_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt
mem_reset_n => slv(mem_in.reset_n), -- .mem_reset_n mem_reset_n => slv(mem4_in.reset_n), -- .mem_reset_n
mem_par => slv(mem_in.par), -- .mem_par mem_par => slv(mem4_in.par), -- .mem_par
sl(mem_alert_n) => mem_ou.alert_n, -- .mem_alert_n sl(mem_alert_n) => mem4_ou.alert_n, -- .mem_alert_n
mem_dqs => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs mem_dqs => mem4_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => mem_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n mem_dqs_n => mem4_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_dq => mem_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq mem_dq => mem4_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dbi_n => mem_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0) -- .mem_dbi_n mem_dbi_n => mem4_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0) -- .mem_dbi_n
); );
END GENERATE; END GENERATE;
......
...@@ -27,7 +27,7 @@ USE technology_lib.technology_pkg.ALL; ...@@ -27,7 +27,7 @@ USE technology_lib.technology_pkg.ALL;
PACKAGE tech_ddr_pkg IS PACKAGE tech_ddr_pkg IS
-- Gather all parameters in one record -- Gather all DDR parameters in one record
TYPE t_c_tech_ddr IS RECORD TYPE t_c_tech_ddr IS RECORD
-- PHY variant within a technology -- PHY variant within a technology
name : STRING(1 TO 4); -- = "DDR3" or "DDR4" name : STRING(1 TO 4); -- = "DDR3" or "DDR4"
...@@ -67,66 +67,82 @@ PACKAGE tech_ddr_pkg IS ...@@ -67,66 +67,82 @@ PACKAGE tech_ddr_pkg IS
-- a a -- a a
-- a row col ba dq dqs dm dbi bg ck cke cs cs_w odt rsl -- a row col ba dq dqs dm dbi bg ck cke cs cs_w odt rsl
CONSTANT c_tech_ddr_max : t_c_tech_ddr := ("none", 800, TRUE, 17, 17, 10, 3, 72, 9, 9, 9, 2, 2, 2, 2, 1, 2, 14, 8, 3, 16, 64, 7); -- maximum ranges for record field definitions CONSTANT c_tech_ddr3_max : t_c_tech_ddr := ("none", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); -- maximum ranges for record field definitions
CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7); CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 0, 0, 2, 2, 2, 1, 2, 14, 4, 2, 4, 64, 7);
CONSTANT c_tech_ddr4_max : t_c_tech_ddr := ("none", 1600, TRUE, 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); -- maximum ranges for record field definitions
CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7); CONSTANT c_tech_ddr4_4g_1600m : t_c_tech_ddr := ("DDR4", 1600, TRUE, 17, 15, 10, 2, 72, 9, 0, 9, 2, 1, 1, 1, 0, 1, 0, 8, 3, 8, 64, 7);
-- PHY in, inout and out signal records -- PHY in, inout and out signal records
TYPE t_tech_ddr_phy_in IS RECORD -- DDR3 DDR4 Description TYPE t_tech_ddr3_phy_in IS RECORD -- DDR3 Description
evt : STD_LOGIC; -- + + event signal is Not Connected to DDR3 PHY evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY
alert_n : STD_LOGIC; -- - + DDR4 alert signal oct_rup : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
oct_rzqin : STD_LOGIC; -- - + DDR4 PHY has On Chip Termination OCT inputs oct_rdn : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
oct_rup : STD_LOGIC; -- + - only master DDR3 PHY has On Chip Termination OCT inputs END RECORD;
oct_rdn : STD_LOGIC; -- + - only master DDR3 PHY has On Chip Termination OCT inputs
TYPE t_tech_ddr4_phy_in IS RECORD -- DDR4 Description
evt : STD_LOGIC; -- event signal
alert_n : STD_LOGIC; -- alert signal
oct_rzqin : STD_LOGIC; -- PHY has On Chip Termination OCT inputs
END RECORD; END RECORD;
TYPE t_tech_ddr_phy_io IS RECORD -- DDR3 DDR4 Description TYPE t_tech_ddr3_phy_io IS RECORD -- DDR3 Description
dq : STD_LOGIC_VECTOR(c_tech_ddr_max.dq_w-1 DOWNTO 0); -- + + data bus dq : STD_LOGIC_VECTOR(c_tech_ddr3_max.dq_w-1 DOWNTO 0); -- data bus
dqs : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0); -- + + data strobe bus dqs : STD_LOGIC_VECTOR(c_tech_ddr3_max.dqs_w-1 DOWNTO 0); -- data strobe bus
dqs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0); -- + - dqs_n : STD_LOGIC_VECTOR(c_tech_ddr3_max.dqs_w-1 DOWNTO 0); -- data strobe bus negative
dbi_n : STD_LOGIC_VECTOR(c_tech_ddr_max.dbi_w-1 DOWNTO 0); -- - + data bus inversion scl : STD_LOGIC; -- I2C clock
scl : STD_LOGIC; -- + - I2C clock sda : STD_LOGIC; -- I2C data
sda : STD_LOGIC; -- + - I2C data
END RECORD; END RECORD;
TYPE t_tech_ddr_phy_ou IS RECORD -- DDR3 DDR4 Description TYPE t_tech_ddr4_phy_io IS RECORD -- DDR4 Description
a : STD_LOGIC_VECTOR(c_tech_ddr_max.a_w-1 DOWNTO 0); -- + + row and column address dq : STD_LOGIC_VECTOR(c_tech_ddr4_max.dq_w-1 DOWNTO 0); -- data bus
ba : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w-1 DOWNTO 0); -- + + bank address dqs : STD_LOGIC_VECTOR(c_tech_ddr4_max.dqs_w-1 DOWNTO 0); -- data strobe bus
dm : STD_LOGIC_VECTOR(c_tech_ddr_max.dm_w-1 DOWNTO 0); -- + - data mask bus dqs_n : STD_LOGIC_VECTOR(c_tech_ddr4_max.dqs_w-1 DOWNTO 0); -- data strobe bus negative
bg : STD_LOGIC_VECTOR(c_tech_ddr_max.bg_w-1 DOWNTO 0); -- - + bank group dbi_n : STD_LOGIC_VECTOR(c_tech_ddr4_max.dbi_w-1 DOWNTO 0); -- data bus inversion
ras_n : STD_LOGIC; -- + a16 row address strobe
cas_n : STD_LOGIC; -- + a15 column address strobe
we_n : STD_LOGIC; -- + a14 write enable signal
act_n : STD_LOGIC; -- - + activate signal
par : STD_LOGIC; -- - + parity signal
reset_n : STD_LOGIC; -- + + reset signal
ck : STD_LOGIC_VECTOR(c_tech_ddr_max.ck_w-1 DOWNTO 0); -- + + clock, positive edge clock
ck_n : STD_LOGIC_VECTOR(c_tech_ddr_max.ck_w-1 DOWNTO 0); -- + + clock, negative edge clock
cke : STD_LOGIC_VECTOR(c_tech_ddr_max.cke_w-1 DOWNTO 0); -- + + clock enable
cs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- + + chip select
odt : STD_LOGIC_VECTOR(c_tech_ddr_max.odt_w-1 DOWNTO 0); -- + + on-die termination control signal
END RECORD; END RECORD;
TYPE t_tech_ddr_phy_terminationcontrol IS RECORD -- DDR3 DDR4 Termination control TYPE t_tech_ddr3_phy_ou IS RECORD -- DDR3 Description
seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- + - termination control from master to slave DDR3 PHY (internal signal in FPGA) a : STD_LOGIC_VECTOR(c_tech_ddr3_max.a_w-1 DOWNTO 0); -- row and column address
parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- + - termination control from master to slave DDR3 PHY (internal signal in FPGA) ba : STD_LOGIC_VECTOR(c_tech_ddr3_max.ba_w-1 DOWNTO 0); -- bank address
dm : STD_LOGIC_VECTOR(c_tech_ddr3_max.dm_w-1 DOWNTO 0); -- data mask bus
ras_n : STD_LOGIC; -- row address strobe
cas_n : STD_LOGIC; -- column address strobe
we_n : STD_LOGIC; -- write enable signal
reset_n : STD_LOGIC; -- reset signal
ck : STD_LOGIC_VECTOR(c_tech_ddr3_max.ck_w-1 DOWNTO 0); -- clock, positive edge clock
ck_n : STD_LOGIC_VECTOR(c_tech_ddr3_max.ck_w-1 DOWNTO 0); -- clock, negative edge clock
cke : STD_LOGIC_VECTOR(c_tech_ddr3_max.cke_w-1 DOWNTO 0); -- clock enable
cs_n : STD_LOGIC_VECTOR(c_tech_ddr3_max.cs_w-1 DOWNTO 0); -- chip select
odt : STD_LOGIC_VECTOR(c_tech_ddr3_max.odt_w-1 DOWNTO 0); -- on-die termination control signal
END RECORD; END RECORD;
CONSTANT c_tech_ddr_phy_terminationcontrol_x : t_tech_ddr_phy_terminationcontrol := ((OTHERS=>'X'), (OTHERS=>'X')); TYPE t_tech_ddr4_phy_ou IS RECORD -- DDR4 Description
CONSTANT c_tech_ddr_phy_terminationcontrol_rst : t_tech_ddr_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0')); a : STD_LOGIC_VECTOR(c_tech_ddr4_max.a_w-1 DOWNTO 0); -- row and column address (note eg. a[16]=ras_n, a[15]=cas_n, a[14]=we_n)
ba : STD_LOGIC_VECTOR(c_tech_ddr4_max.ba_w-1 DOWNTO 0); -- bank address
bg : STD_LOGIC_VECTOR(c_tech_ddr4_max.bg_w-1 DOWNTO 0); -- bank group
act_n : STD_LOGIC; -- activate signal
par : STD_LOGIC; -- parity signal
reset_n : STD_LOGIC; -- reset signal
ck : STD_LOGIC_VECTOR(c_tech_ddr4_max.ck_w-1 DOWNTO 0); -- clock, positive edge clock
ck_n : STD_LOGIC_VECTOR(c_tech_ddr4_max.ck_w-1 DOWNTO 0); -- clock, negative edge clock
cke : STD_LOGIC_VECTOR(c_tech_ddr4_max.cke_w-1 DOWNTO 0); -- clock enable
cs_n : STD_LOGIC_VECTOR(c_tech_ddr4_max.cs_w-1 DOWNTO 0); -- chip select
odt : STD_LOGIC_VECTOR(c_tech_ddr4_max.odt_w-1 DOWNTO 0); -- on-die termination control signal
END RECORD;
TYPE t_tech_ddr3_phy_terminationcontrol IS RECORD -- DDR3 Termination control
seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr3_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
END RECORD;
CONSTANT c_tech_ddr_phy_in_x : t_tech_ddr_phy_in := ('X', 'X', 'X', 'X', 'X'); CONSTANT c_tech_ddr3_phy_terminationcontrol_x : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'X'), (OTHERS=>'X'));
CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', '1', 'X', 'X', 'X'); CONSTANT c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0'));
CONSTANT c_tech_ddr_phy_io_x : t_tech_ddr_phy_io := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X');
CONSTANT c_tech_ddr_phy_io_rst : t_tech_ddr_phy_io := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
CONSTANT c_tech_ddr_phy_ou_x : t_tech_ddr_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
CONSTANT c_tech_ddr_phy_ou_rst : t_tech_ddr_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
TYPE t_tech_ddr_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_in; CONSTANT c_tech_ddr3_phy_in_x : t_tech_ddr3_phy_in := ('X', 'X', 'X');
TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io; CONSTANT c_tech_ddr4_phy_in_x : t_tech_ddr4_phy_in := ('X', 'X', 'X');
TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou; CONSTANT c_tech_ddr3_phy_ou_x : t_tech_ddr3_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
TYPE t_tech_ddr_phy_terminationcontrol_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_terminationcontrol; CONSTANT c_tech_ddr4_phy_ou_x : t_tech_ddr4_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
END tech_ddr_pkg; END tech_ddr_pkg;
......
...@@ -59,13 +59,13 @@ ENTITY tech_ddr_stratixiv IS ...@@ -59,13 +59,13 @@ ENTITY tech_ddr_stratixiv IS
ctlr_mosi : IN t_mem_ctlr_mosi; ctlr_mosi : IN t_mem_ctlr_mosi;
ctlr_miso : OUT t_mem_ctlr_miso; ctlr_miso : OUT t_mem_ctlr_miso;
term_ctrl_out : OUT t_tech_ddr_phy_terminationcontrol; term_ctrl_out : OUT t_tech_ddr3_phy_terminationcontrol;
term_ctrl_in : IN t_tech_ddr_phy_terminationcontrol := c_tech_ddr_phy_terminationcontrol_rst; term_ctrl_in : IN t_tech_ddr3_phy_terminationcontrol := c_tech_ddr3_phy_terminationcontrol_rst;
-- PHY interface -- PHY interface
phy_in : IN t_tech_ddr_phy_in; phy_in : IN t_tech_ddr3_phy_in;
phy_io : INOUT t_tech_ddr_phy_io; phy_io : INOUT t_tech_ddr3_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou phy_ou : OUT t_tech_ddr3_phy_ou
); );
END tech_ddr_stratixiv; END tech_ddr_stratixiv;
......
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