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Commit 3f77bc82 authored by Eric Kooistra's avatar Eric Kooistra
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Use phy records from tech_ddr_lib.tech_ddr_pkg.

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libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+ 7
− 6
View file @ 3f77bc82
......@@ -39,13 +39,14 @@
-- gives an error at the end of the write cyclus.
--
LIBRARY IEEE, common_lib, dp_lib, diagnostics_lib;
LIBRARY IEEE, tech_ddr_lib, common_lib, dp_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_ddr3 IS
......@@ -94,9 +95,9 @@ ARCHITECTURE str of tb_ddr3 IS
SIGNAL snk_diag_res_val : STD_LOGIC;
SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL phy_in : t_tech_ddr3_phy_in;
SIGNAL phy_io : t_tech_ddr3_phy_io;
SIGNAL phy_ou : t_tech_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -220,8 +221,8 @@ BEGIN
PORT MAP (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
mem_ba => phy_ou.ba, -- .mem_ba
mem_ck => phy_io.clk, -- .mem_ck
mem_ck_n => phy_io.clk_n, -- .mem_ck_n
mem_ck => phy_ou.ck, -- .mem_ck
mem_ck_n => phy_ou.ck_n, -- .mem_ck_n
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_dm => phy_ou.dm, -- .mem_dm
......
libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+ 14
− 7
View file @ 3f77bc82
......@@ -31,7 +31,7 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
LIBRARY IEEE, tech_ddr_lib, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -43,6 +43,7 @@ USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_ddr3_transpose IS
......@@ -179,9 +180,9 @@ ARCHITECTURE tb OF tb_ddr3_transpose IS
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL phy_in : t_tech_ddr3_phy_in;
SIGNAL phy_io : t_tech_ddr3_phy_io;
SIGNAL phy_ou : t_tech_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -287,9 +288,15 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_ref_clk => dp_clk,
dp_ref_rst => dp_rst,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_out_clk => OPEN,
dp_out_rst => OPEN,
snk_out_arr => bg_siso_arr,
snk_in_arr => bg_sosi_arr,
-- ST source
......@@ -341,8 +348,8 @@ BEGIN
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_ck => phy_ou.ck,
mem_ck_n => phy_ou.ck_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
......
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+ 7
− 6
View file @ 3f77bc82
......@@ -31,7 +31,7 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
LIBRARY IEEE, tech_ddr_lib, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -43,6 +43,7 @@ USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_mms_ddr3 IS
......@@ -163,9 +164,9 @@ ARCHITECTURE tb OF tb_mms_ddr3 IS
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL phy_in : t_tech_ddr3_phy_in;
SIGNAL phy_io : t_tech_ddr3_phy_io;
SIGNAL phy_ou : t_tech_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -336,8 +337,8 @@ BEGIN
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_ck => phy_ou.ck,
mem_ck_n => phy_ou.ck_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
......
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+ 7
− 6
View file @ 3f77bc82
......@@ -31,7 +31,7 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
LIBRARY IEEE, tech_ddr_lib, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -43,6 +43,7 @@ USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_seq_ddr3 IS
......@@ -172,9 +173,9 @@ ARCHITECTURE tb OF tb_seq_ddr3 IS
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL phy_in : t_tech_ddr3_phy_in;
SIGNAL phy_io : t_tech_ddr3_phy_io;
SIGNAL phy_ou : t_tech_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -319,8 +320,8 @@ BEGIN
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_ck => phy_ou.ck,
mem_ck_n => phy_ou.ck_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
......
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