Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more...

Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more clearly distinghuis it from ctrl_drv_mosi for the IO driver side.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -78,7 +78,7 @@
 --
 -- Block diagram:
 --
---                          ctlr_wr_fifo_src      ctlr_wr_snk   ctlr_mosi
+--                          ctlr_wr_fifo_src      ctlr_wr_snk   ctlr_tech_mosi
 --                      ________      .   ______    .   _______   .   ______
 --   wr_fifo_usedw <---|dp_fifo |     .  |dp    |   .  |       |  .  |      |
 --   wr_sosi --------->|dc_mixed|-+----->|flush |----->| io    |  .  | tech |
@@ -103,7 +103,7 @@
 --   rd_sosi <---------|dc_mixed|<---------------------|       |  .  |      |
 --   rd_fifo_usedw <---|widths  |                   .  |_______|  .  |______|---\
 --                     |________|                   .             .             |
---                                                ctlr_rd_src   ctlr_miso       |
+--                                                ctlr_rd_src   ctlr_tech_miso  |
 --                                                                              |
 --   ctlr_clk /------ctlr_clk_in ------->                                       |
 --            \------ctlr_clk_out-----------------------------------------------/
@@ -243,8 +243,8 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_dvr_miso         : t_mem_ctlr_miso;
   SIGNAL ctlr_dvr_mosi         : t_mem_ctlr_mosi;
     
-  SIGNAL ctlr_mosi             : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
-  SIGNAL ctlr_miso             : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
+  SIGNAL ctlr_tech_mosi        : t_mem_ctlr_mosi := c_mem_ctlr_mosi_rst;
+  SIGNAL ctlr_tech_miso        : t_mem_ctlr_miso := c_mem_ctlr_miso_rst;
 
   SIGNAL ctlr_wr_flush_en      : STD_LOGIC := '0';
  
@@ -431,8 +431,8 @@ BEGIN
     rd_src_out => ctlr_rd_src_out,
     rd_src_in  => ctlr_rd_src_in,
 
-    ctlr_miso  => ctlr_miso,
-    ctlr_mosi  => ctlr_mosi
+    ctlr_miso  => ctlr_tech_miso,
+    ctlr_mosi  => ctlr_tech_mosi
   );
   
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
@@ -443,8 +443,8 @@ BEGIN
   )
   PORT MAP (
     -- PLL reference clock
-    ctlr_ref_clk    => ctlr_ref_clk,
-    ctlr_ref_rst    => ctlr_ref_rst,
+    ref_clk         => ctlr_ref_clk,
+    ref_rst         => ctlr_ref_rst,
 
     -- Controller user interface
     ctlr_gen_clk    => ctlr_clk_out,
@@ -452,8 +452,8 @@ BEGIN
     ctlr_gen_clk_2x => OPEN,
     ctlr_gen_rst_2x => OPEN,
 
-    ctlr_mosi       => ctlr_mosi,
-    ctlr_miso       => ctlr_miso,
+    ctlr_mosi       => ctlr_tech_mosi,
+    ctlr_miso       => ctlr_tech_miso,
 
     term_ctrl_out   => term_ctrl_out,
     term_ctrl_in    => term_ctrl_in,
@@ -465,7 +465,7 @@ BEGIN
   );  
   
   ctlr_rst_out  <= ctlr_rst_out_i;
-  mm_reg_io_ddr <= RESIZE_UVEC(ctlr_rst_out_i & ctlr_mosi.flush & ctlr_miso.waitrequest_n & ctlr_miso.done, 32);   
+  mm_reg_io_ddr <= RESIZE_UVEC(ctlr_rst_out_i & ctlr_tech_mosi.flush & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, 32);   
   
   u_reg_map : ENTITY common_lib. common_reg_r_w_dc
   GENERIC MAP (