Added default values to mm_Rst and mm_clk

libraries/io/ddr3/src/vhdl/ddr3.vhd

@@ -48,8 +48,8 @@ ENTITY ddr3 IS
   );                      
   PORT (   
     -- MM clock + reset                                                             
-    mm_rst             : IN    STD_LOGIC;                                           
-    mm_clk             : IN    STD_LOGIC;                                                          
+    mm_rst             : IN    STD_LOGIC := '0';                                           
+    mm_clk             : IN    STD_LOGIC := '0';                                                          
     
     ctlr_ref_clk       : IN    STD_LOGIC;
     ctlr_rst           : IN    STD_LOGIC; -- asynchronous reset input to controller