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Commit f1cda4e0 authored by Eric Kooistra's avatar Eric Kooistra
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Rename ctlr_ref_clk into ref_clk to have simpler and more clear name.

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libraries/technology/ddr/tech_ddr.vhd
+ 4
− 4
View file @ f1cda4e0
......@@ -45,8 +45,8 @@ ENTITY tech_ddr IS
);
PORT (
-- PLL reference clock
ctlr_ref_clk : IN STD_LOGIC;
ctlr_ref_rst : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
ref_rst : IN STD_LOGIC;
-- Controller user interface
ctlr_gen_clk : OUT STD_LOGIC;
......@@ -77,7 +77,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_ddr_stratixiv
GENERIC MAP (g_tech_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_mosi, ctlr_miso, term_ctrl_out, term_ctrl_in,
phy_in, phy_io, i_phy_ou);
......@@ -86,7 +86,7 @@ BEGIN
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ENTITY work.tech_ddr_arria10
GENERIC MAP (g_tech_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
PORT MAP (ref_clk, ref_rst,
ctlr_gen_clk, ctlr_gen_rst,
ctlr_mosi, ctlr_miso,
phy_in, phy_io, i_phy_ou);
......
libraries/technology/ddr/tech_ddr_arria10.vhd
+ 7
− 7
View file @ f1cda4e0
......@@ -50,8 +50,8 @@ ENTITY tech_ddr_arria10 IS
);
PORT (
-- PLL reference clock
ctlr_ref_clk : IN STD_LOGIC;
ctlr_ref_rst : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
ref_rst : IN STD_LOGIC;
-- Controller user interface
ctlr_gen_clk : OUT STD_LOGIC;
......@@ -76,7 +76,7 @@ ARCHITECTURE str OF tech_ddr_arria10 IS
CONSTANT c_ctlr_data_w : NATURAL := 576;--func_tech_ddr_ctlr_data_w( g_tech_ddr);
SIGNAL i_ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_ref_rst_n : STD_LOGIC;
SIGNAL ref_rst_n : STD_LOGIC;
SIGNAL ctlr_gen_rst_n : STD_LOGIC := '0';
SIGNAL local_cal_success : STD_LOGIC;
......@@ -86,8 +86,8 @@ BEGIN
ctlr_gen_clk <= i_ctlr_gen_clk;
ctlr_ref_rst_n <= NOT ctlr_ref_rst;
ctlr_gen_rst <= NOT ctlr_gen_rst_n;
ref_rst_n <= NOT ref_rst;
ctlr_gen_rst <= NOT ctlr_gen_rst_n;
gen_ip_arria10_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
u_ip_arria10_ddr4_4g_1600 : ip_arria10_ddr4_4g_1600
......@@ -103,7 +103,7 @@ BEGIN
amm_readdatavalid_0 => ctlr_miso.rdval, -- .readdatavalid
emif_usr_clk => i_ctlr_gen_clk, -- emif_usr_clk_clock_source.clk
emif_usr_reset_n => ctlr_gen_rst_n, -- emif_usr_reset_reset_source.reset_n
global_reset_n => ctlr_ref_rst_n, -- global_reset_reset_sink.reset_n
global_reset_n => ref_rst_n, -- global_reset_reset_sink.reset_n
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- mem_conduit_end.mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_a => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0), -- .mem_a
......@@ -121,7 +121,7 @@ BEGIN
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dbi_n => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0), -- .mem_dbi_n
oct_rzqin => phy_in.oct_rzqin, -- oct_conduit_end.oct_rzqin
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk_clock_sink.clk
pll_ref_clk => ref_clk, -- pll_ref_clk_clock_sink.clk
local_cal_success => local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => local_cal_fail -- .local_cal_fail
);
......
libraries/technology/ddr/tech_ddr_stratixiv.vhd
+ 9
− 9
View file @ f1cda4e0
......@@ -47,8 +47,8 @@ ENTITY tech_ddr_stratixiv IS
);
PORT (
-- PLL reference clock
ctlr_ref_clk : IN STD_LOGIC;
ctlr_ref_rst : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
ref_rst : IN STD_LOGIC;
-- Controller user interface
ctlr_gen_clk : OUT STD_LOGIC;
......@@ -79,20 +79,20 @@ ARCHITECTURE str OF tech_ddr_stratixiv IS
SIGNAL dbg_c_gigabytes : NATURAL := c_gigabytes;
SIGNAL ctlr_ref_rst_n : STD_LOGIC;
SIGNAL ref_rst_n : STD_LOGIC;
SIGNAL ctlr_gen_rst_n : STD_LOGIC;
SIGNAL i_ctlr_gen_rst : STD_LOGIC;
SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
BEGIN
ctlr_ref_rst_n <= NOT ctlr_ref_rst;
ref_rst_n <= NOT ref_rst;
gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
global_reset_n => ctlr_ref_rst_n, -- global_reset.reset_n
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
global_reset_n => ref_rst_n, -- global_reset.reset_n
soft_reset_n => '1', -- soft_reset.reset_n
afi_clk => ctlr_gen_clk, -- afi_clk.clk
afi_half_clk => OPEN, -- afi_half_clk.clk
......@@ -143,8 +143,8 @@ BEGIN
gen_ip_stratixiv_ddr3_uphy_4g_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP (
pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
global_reset_n => ctlr_ref_rst_n, -- global_reset.reset_n
pll_ref_clk => ref_clk, -- pll_ref_clk.clk
global_reset_n => ref_rst_n, -- global_reset.reset_n
soft_reset_n => '1', -- soft_reset.reset_n
afi_clk => ctlr_gen_clk, -- afi_clk.clk
afi_half_clk => OPEN, -- afi_half_clk.clk
......@@ -197,7 +197,7 @@ BEGIN
g_rst_level => '0'
)
PORT MAP(
rst => ctlr_ref_rst,
rst => ref_rst,
clk => i_ctlr_gen_clk_2x,
din => i_ctlr_gen_rst,
dout => ctlr_gen_rst_2x
......
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