Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr = TRUE to get between mm_clk and ctlr_clk_in.

Removed clock domain crossing logic for this control register, because that is done by io_ddr_cross_domain.vhd in io_ddr.vhd. Removed cal_fail and cal_ok, because these are already available via the io_ddr status register.

Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and IO_DDR as is and it compiles.

Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified in the uniphy emi_ip.pdf manual.

-Enabled this model in tb_apertif_unb1_fn_beamformer_tp_bg.

- Switched fail and ok in reg map
- Removed comments  

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more clearly distinghuis it from ctrl_drv_mosi for the IO driver side.

splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst accesses of g_tech_ddr.maxburstsize each.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Only need to reset the state reg, do not reset the other signals to easy timing closure. Use natural for burst_wr_cnt instead of slv.