Default ctlr_mosi.burstsize <= burst_size fits all states.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -170,8 +170,8 @@ BEGIN
     ctlr_mosi.wr           <= '0';
     ctlr_mosi.rd           <= '0';
     ctlr_mosi.burstbegin   <= '0';                                   -- only used for legacy DDR controllers, because the controller can derive it internally by counting wr and rd accesses
-    ctlr_mosi.burstsize    <= (OTHERS => '0');                       -- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
-    
+    ctlr_mosi.burstsize    <= TO_MEM_CTLR_BURSTSIZE(burst_size);     -- burstsize >= 1,
+                                                                     -- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
     wr_snk_out.ready       <= '0';
     nxt_dvr_done           <= '0';
     nxt_cur_address        <= cur_address;
@@ -202,7 +202,6 @@ BEGIN
             wr_snk_out.ready     <= '1';
             ctlr_mosi.wr         <= '1';
             ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
-            ctlr_mosi.burstsize  <= TO_MEM_CTLR_BURSTSIZE(burst_size);  -- burstsize >= 1
             nxt_cur_address      <= INCR_UVEC(cur_address, burst_size);
             nxt_address_cnt      <= INCR_UVEC(address_cnt, -burst_size);
             nxt_burst_wr_cnt     <= burst_size-1;
@@ -218,19 +217,16 @@ BEGIN
         IF address_cnt_is_0 = '1' THEN  -- end address reached
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;
-        ELSE 
+        ELSIF ctlr_miso.waitrequest_n = '1' THEN
           IF rd_src_in.ready = '1' THEN  -- the external FIFO uses almost full level assert its snk_out.ready and can then still accept the maximum rd burst of words
-            IF ctlr_miso.waitrequest_n = '1' THEN    
             ctlr_mosi.rd         <= '1';                   
             ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
-              ctlr_mosi.burstsize  <= TO_MEM_CTLR_BURSTSIZE(burst_size);  -- burstsize >= 1
             nxt_cur_address      <= INCR_UVEC(cur_address, burst_size);  
             nxt_address_cnt      <= INCR_UVEC(address_cnt, -burst_size);
             -- Return for next rd request
             nxt_state <= s_wait;
           END IF;           
         END IF; 
-        END IF; 
 
       -- In this state address_cnt is valid and in the next state burst_size (that depends on address_cnt) will be valid.
       -- Therefore this wait state is inserted between any requests.