Cosmetic.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -180,7 +180,7 @@ BEGIN
 
     CASE state IS
      
-      WHEN s_wr_burst => -- Performs the burst portion (word 2+)        
+      WHEN s_wr_burst => -- Performs the rest of burst when burst_size > 1
         IF ctlr_miso.waitrequest_n = '1' THEN
           IF wr_snk_in.valid = '1' THEN         -- it is allowed that valid is not always active during a burst
             wr_snk_out.ready <= '1';            -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
@@ -190,9 +190,9 @@ BEGIN
               nxt_state <= s_wr_request;        -- initiate a new wr burst or goto idle via the wr_request state, simulation shows going directly idle by checking address_cnt_is_0 here does not save a cycle
             END IF;
           END IF;
-        END IF;            
+        END IF;
 
-      WHEN s_wr_request =>  -- Performs 1 write access and goes into s_wr_burst when requested write words >1       
+      WHEN s_wr_request =>  -- Performs 1 write access and goes into s_wr_burst when requested burst_size >1       
         IF address_cnt_is_0 = '1' THEN  -- end address reached
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;