Added g_sim, when TRUE then use internal DDR memory model in tech_ddr...

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -41,6 +41,10 @@
 --   DDR write access can start on the next valid, sop or sync dependent on
 --   g_wr_flush_mode.
 --
+--   In simulation use g_sim=TRUE to also include the DDR memory model that is
+--   internally available within tech_ddr. This avoids having to connect a DDR
+--   memory model at top level in the test bench.
+--
 -- Usage:
 -- . The dvr interface could be connected to a MM register. The DDR memory
 --   may then be used to capture (large) blocks of streaming data that can
@@ -126,6 +130,7 @@ ENTITY io_ddr IS
   GENERIC(
     g_technology              : NATURAL := c_tech_select_default;
     g_tech_ddr                : t_c_tech_ddr;
+    g_sim                     : BOOLEAN := FALSE;   -- when TRUE use internal DDR memory model
     g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;
     g_wr_data_w               : NATURAL := 32;  
     g_wr_fifo_depth           : NATURAL := 128;     -- >=16                             , defined at DDR side of the FIFO.
@@ -172,7 +177,7 @@ ENTITY io_ddr IS
     rd_siso            : IN    t_dp_siso;
     
     -- DDR PHY external interface
-    phy_in             : IN    t_tech_ddr_phy_in;
+    phy_in             : IN    t_tech_ddr_phy_in := c_tech_ddr_phy_in_x;
     phy_io             : INOUT t_tech_ddr_phy_io;
     phy_ou             : OUT   t_tech_ddr_phy_ou
   );
@@ -384,7 +389,8 @@ BEGIN
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
   GENERIC MAP (
     g_technology => g_technology,
-    g_tech_ddr   => g_tech_ddr
+    g_tech_ddr   => g_tech_ddr,
+    g_sim        => g_sim
   )
   PORT MAP (
     -- PLL reference clock

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -47,8 +47,9 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
 ENTITY tb_io_ddr IS
   GENERIC (
     g_technology            : NATURAL := c_tech_select_default;
+    g_sim                   : BOOLEAN := TRUE;  -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
     g_ctlr_ref_clk_period   : TIME := 5 ns;     -- 200 MHz
-    g_dvr_clk_period        : TIME := 5 ns;    -- 50 ns
+    g_dvr_clk_period        : TIME := 5 ns;     -- 50 ns
     g_dp_clk_period         : TIME := 5000 ps;  -- 200 MHz
     g_dp_data_w             : NATURAL := 32;    -- 32 for mixed width and 256 for equal width FIFO
     g_nof_repeat            : NATURAL := 2;
@@ -123,6 +124,7 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL snk_val_cnt          : STD_LOGIC_VECTOR(31 DOWNTO 0);
   SIGNAL expected_cnt         : NATURAL;
   
+  -- PHY interface
   SIGNAL phy_in               : t_tech_ddr_phy_in;
   SIGNAL phy_io               : t_tech_ddr_phy_io;
   SIGNAL phy_ou               : t_tech_ddr_phy_ou;
@@ -270,6 +272,7 @@ BEGIN
   GENERIC MAP(
     g_technology             => g_technology,
     g_tech_ddr               => c_tech_ddr,
+    g_sim                    => g_sim,            -- when TRUE use internal DDR memory model
     g_cross_domain_dvr_ctlr  => c_cross_domain_dvr_ctlr,
     g_wr_data_w              => g_dp_data_w,
     g_wr_fifo_depth          => c_wr_fifo_depth,  -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO.
@@ -320,16 +323,18 @@ BEGIN
     phy_io             => phy_io,
     phy_in             => phy_in
   );
- 
-  u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
-  GENERIC MAP (
-    g_tech_ddr => c_tech_ddr
-  )
-  PORT MAP (
-    mem_in => phy_ou,
-    mem_io => phy_io
-  );
-    
+  
+  external_ddr_memory_model : IF g_sim=FALSE GENERATE
+    u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+    GENERIC MAP (
+      g_tech_ddr => c_tech_ddr
+    )
+    PORT MAP (
+      mem_in => phy_ou,
+      mem_io => phy_io
+    );
+  END GENERATE;
+     
 END ARCHITECTURE str;
 
 

libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd

@@ -40,6 +40,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
 BEGIN
 
   -- g_technology           : NATURAL := c_tech_select_default;
+  -- g_sim                  : BOOLEAN := TRUE;  -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
   -- g_ctlr_ref_clk_period  : TIME := 5 ns;     -- 200 MHz
   -- g_dvr_clk_period       : TIME := 20 ns;    -- 50 ns
   -- g_dp_clk_period        : TIME := 5000 ps;  -- 200 MHz
@@ -47,13 +48,14 @@ BEGIN
   -- g_nof_repeat           : NATURAL := 2;
   -- g_wr_flush_mode        : STRING := "SYN"  -- "VAL", "SOP", "SYN"
 
-  u_fill_wrfifo_on_next_valid     : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns,  5 ns, 5 ns, 256, 2, "VAL");
-  u_fill_wrfifo_on_next_sop       : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns,  5 ns, 5 ns, 256, 2, "SOP");
-  u_fill_wrfifo_on_next_sync      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns,  5 ns, 5 ns, 256, 2, "SYN");
+  u_fill_wrfifo_on_next_valid     : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "VAL");
+  u_fill_wrfifo_on_next_sop       : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SOP");
+  u_fill_wrfifo_on_next_sync      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns, 256, 2, "SYN");
   
-  u_mixed_width                   : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns,  5 ns, 5 ns,  32, 1, "VAL");
+  u_ext_memory_model              : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default,  TRUE, 5 ns,  5 ns, 5 ns, 256, 1, "VAL");
+  u_mixed_width                   : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  5 ns, 5 ns,  32, 1, "VAL");
   
-  u_cross_dvr_to_faster_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns, 20 ns, 5 ns, 256, 1, "VAL");
-  u_cross_dvr_to_slower_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, 5 ns,  1 ns, 5 ns, 256, 1, "VAL");
+  u_cross_dvr_to_faster_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns, 20 ns, 5 ns, 256, 1, "VAL");
+  u_cross_dvr_to_slower_ctlr      : ENTITY work.tb_io_ddr GENERIC MAP (c_tech_select_default, FALSE, 5 ns,  1 ns, 5 ns, 256, 1, "VAL");
   
 END tb;

libraries/technology/ddr/tech_ddr.vhd

@@ -23,18 +23,23 @@
 -- Purpose: Technology independent component for DDR memory access.
 -- Description:
 --   The component also supports different types of DDR, so DDR3 and DDR4.
+-- Remark:
+--   In simulation use g_sim=TRUE to also include the DDR memory model that is
+--   internally available within tech_ddr. This avoids having to connect a DDR
+--   memory model at top level in the test bench.
 
-LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE work.tech_ddr_pkg.ALL;
 
 ENTITY tech_ddr IS
   GENERIC (
     g_technology : NATURAL := c_tech_select_default;
-    g_tech_ddr   : t_c_tech_ddr
+    g_tech_ddr   : t_c_tech_ddr;
+    g_sim        : BOOLEAN := FALSE
   );
   PORT (
     -- PLL reference clock
@@ -60,6 +65,8 @@ END tech_ddr;
 
 ARCHITECTURE str OF tech_ddr IS
 
+  SIGNAL i_phy_ou     : t_tech_ddr_phy_ou;
+  
 BEGIN
  
   gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
@@ -68,7 +75,23 @@ BEGIN
     PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
               ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
               ctlr_mosi, ctlr_miso,
-              phy_in, phy_io, phy_ou);
+              phy_in, phy_io, i_phy_ou);
+  END GENERATE;
+  
+  -- Include DDR memory model for simulation
+  no_sim : IF g_sim=FALSE GENERATE
+    phy_ou <= i_phy_ou;
+  END GENERATE;
+  
+  gen_sim: IF g_sim=TRUE GENERATE
+    u_tech_ddr_memory_model : ENTITY work.tech_ddr_memory_model
+    GENERIC MAP (
+      g_tech_ddr => g_tech_ddr
+    )
+    PORT MAP (
+      mem_in => i_phy_ou,
+      mem_io => phy_io
+    );
   END GENERATE;
   
 END str;