Renamed g_sim into g_use_ddr_memory_model.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -49,9 +49,9 @@
 --   bursts already be pending. Therefore the g_rd_fifo_af_margin needs to be
 --   large enough to fit a number of read bursts.
 
---   In simulation use g_sim=TRUE to also include the DDR memory model that is
---   internally available within tech_ddr. This avoids having to connect a DDR
---   memory model at top level in the test bench.
+--   In simulation use g_use_ddr_memory_model=TRUE to also include the DDR
+--   memory model that is internally available within tech_ddr. This avoids
+--   having to connect a DDR memory model at top level in the test bench.
 --
 -- Usage:
 -- . The dvr interface could be connected to a MM register. The DDR memory
@@ -160,7 +160,7 @@ ENTITY io_ddr IS
   GENERIC(
     g_technology              : NATURAL := c_tech_select_default;
     g_tech_ddr                : t_c_tech_ddr;
-    g_sim                     : BOOLEAN := FALSE;   -- when TRUE use internal DDR memory model
+    g_use_ddr_memory_model    : BOOLEAN := FALSE;   -- when TRUE use internal DDR memory model, else connect DDR memory model in top level tb
     g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;
     g_cross_domain_delay_len  : NATURAL := c_meta_delay_len;
     g_wr_data_w               : NATURAL := 32;  
@@ -423,9 +423,9 @@ BEGIN
   
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
   GENERIC MAP (
-    g_technology => g_technology,
-    g_tech_ddr   => g_tech_ddr,
-    g_sim        => g_sim
+    g_technology           => g_technology,
+    g_tech_ddr             => g_tech_ddr,
+    g_use_ddr_memory_model => g_use_ddr_memory_model
   )
   PORT MAP (
     -- PLL reference clock

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -48,7 +48,7 @@ ENTITY tb_io_ddr IS
     g_tech_ddr3             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
     g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
     g_tb_end                : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-    g_sim                   : BOOLEAN := FALSE;   -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
+    g_use_ddr_memory_model  : BOOLEAN := FALSE;  -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
     g_cross_domain_dvr_ctlr : BOOLEAN := FALSE;  -- when TRUE insert clock cross domain logic
     g_ctlr_ref_clk_period   : TIME := 5000 ps;   -- 200 MHz
     g_dvr_clk_period        : TIME := 5000 ps;   -- 50 MHz
@@ -390,7 +390,7 @@ BEGIN
   GENERIC MAP(
     g_technology             => g_technology,
     g_tech_ddr               => c_tech_ddr,
-    g_sim                    => g_sim,            -- when TRUE use internal DDR memory model
+    g_use_ddr_memory_model   => g_use_ddr_memory_model,   -- when TRUE use internal DDR memory model
     g_cross_domain_dvr_ctlr  => c_cross_domain_dvr_ctlr,
     g_cross_domain_delay_len => c_meta_delay_len,
     g_wr_data_w              => c_dp_data_w,
@@ -444,7 +444,7 @@ BEGIN
     phy_in             => phy_in
   );
   
-  external_ddr_memory_model : IF g_sim=FALSE GENERATE
+  external_ddr_memory_model : IF g_use_ddr_memory_model=FALSE GENERATE
     u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
     GENERIC MAP (
       g_sim      => TRUE,

libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd

@@ -52,7 +52,7 @@ BEGIN
   -- g_tech_ddr3             : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
   -- g_tech_ddr4             : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
   -- g_tb_end                : BOOLEAN := TRUE;   -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-  -- g_sim                   : BOOLEAN := TRUE;   -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
+  -- g_use_ddr_memory_model  : BOOLEAN := TRUE;   -- when TRUE use the internal DDR memory model, else use the DDR model in this tb.
   -- g_cross_domain_dvr_ctlr : BOOLEAN := FALSE;  -- when TRUE insert clock cross domain logic
   -- g_ctlr_ref_clk_period   : TIME := 5 ns;      -- 200 MHz
   -- g_dvr_clk_period        : TIME := 5 ns;      -- 50 ns