Imporved g_sim_model description comment.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -154,7 +154,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY io_ddr IS
   GENERIC(
-    g_sim_model               : BOOLEAN := FALSE;
+    g_sim_model               : BOOLEAN := FALSE;   -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
     g_technology              : NATURAL := c_tech_select_default;
     g_tech_ddr                : t_c_tech_ddr;
     g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;    -- use TRUE when MM clock is used for the access control, use FALSE when ctlr_clk_in=ctlr_clk_out is used to avoid extra latency

libraries/technology/ddr/tech_ddr.vhd

@@ -35,7 +35,7 @@ USE work.tech_ddr_pkg.ALL;
 
 ENTITY tech_ddr IS
   GENERIC (
-    g_sim_model            : BOOLEAN := FALSE;  -- TRUE: use fast behavioural model, requires no external memory (uses memory array).
+    g_sim_model            : BOOLEAN := FALSE;  -- when FALSE use IP and external DDR3 model, else when TRUE: use fast behavioural model, requires no external memory (uses memory array).
     g_technology           : NATURAL := c_tech_select_default;
     g_tech_ddr             : t_c_tech_ddr
   );