Corrected use of ctrl_miso.waitrequest_n to avoid combinational loop with ctrl_mosi.wr and rd.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -182,10 +182,10 @@ BEGIN
     CASE state IS
      
       WHEN s_wr_burst => -- Performs the rest of burst when burst_size > 1
-        IF ctlr_miso.waitrequest_n = '1' THEN
-          IF wr_snk_in.valid = '1' THEN         -- it is allowed that valid is not always active during a burst
+        IF wr_snk_in.valid = '1' THEN         -- it is allowed that valid is not always active during a burst
+          ctlr_mosi.wr <= '1';
+          IF ctlr_miso.waitrequest_n = '1' THEN
             wr_snk_out.ready <= '1';            -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
-            ctlr_mosi.wr     <= '1';
             nxt_burst_wr_cnt <= burst_wr_cnt-1;
             IF burst_wr_cnt = 1 THEN            -- check for the last cycle of this burst sequence
               nxt_state <= s_wr_request;        -- initiate a new wr burst or goto idle via the wr_request state, simulation shows going directly idle by checking address_cnt_is_0 here does not save a cycle
@@ -197,12 +197,12 @@ BEGIN
         IF address_cnt_is_0 = '1' THEN  -- end address reached
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;
-        ELSIF ctlr_miso.waitrequest_n = '1' THEN 
-          IF wr_snk_in.valid = '1' THEN
+        ELSIF wr_snk_in.valid = '1' THEN
+          ctlr_mosi.wr         <= '1';
+          ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
+          IF ctlr_miso.waitrequest_n = '1' THEN 
             -- Always perform 1st write here             
             wr_snk_out.ready     <= '1';
-            ctlr_mosi.wr         <= '1';
-            ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
             nxt_cur_address      <= INCR_UVEC(cur_address, burst_size);
             nxt_address_cnt      <= INCR_UVEC(address_cnt, -burst_size);
             nxt_burst_wr_cnt     <= burst_size-1;
@@ -218,10 +218,10 @@ BEGIN
         IF address_cnt_is_0 = '1' THEN  -- end address reached
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;
-        ELSIF ctlr_miso.waitrequest_n = '1' THEN
-          IF rd_src_in.ready = '1' THEN  -- the external FIFO uses almost full level assert its snk_out.ready and can then still accept the maximum rd burst of words
-            ctlr_mosi.rd         <= '1';                   
-            ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
+        ELSIF rd_src_in.ready = '1' THEN  -- the external FIFO uses almost full level assert its snk_out.ready and can then still accept the maximum rd burst of words
+          ctlr_mosi.rd         <= '1';                   
+          ctlr_mosi.burstbegin <= '1';                                -- assert burstbegin,
+          IF ctlr_miso.waitrequest_n = '1' THEN
             nxt_cur_address      <= INCR_UVEC(cur_address, burst_size);  
             nxt_address_cnt      <= INCR_UVEC(address_cnt, -burst_size);
             -- Return for next rd request