Added register map for io_ddr ctrol signals.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -185,6 +185,14 @@ ENTITY io_ddr IS
     ctlr_clk_in        : IN    STD_LOGIC;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        : IN    STD_LOGIC;  -- connect ctlr_rst_out to ctlr_rst_in at top level
     
+    -- MM clock + reset
+    mm_rst             : IN    STD_LOGIC;                                           
+    mm_clk             : IN    STD_LOGIC; 
+    
+    -- MM register map for DDR controller status info
+    reg_io_ddr_mosi    : IN    t_mem_mosi;
+    reg_io_ddr_miso    : OUT   t_mem_miso;
+    
     -- Driver clock domain
     dvr_clk            : IN    STD_LOGIC;
     dvr_rst            : IN    STD_LOGIC;
@@ -230,6 +238,7 @@ ARCHITECTURE str OF io_ddr IS
   CONSTANT c_wr_fifo_depth     : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w);  -- get FIFO depth at write side
   
   CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1;                        -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
+  CONSTANT c_mem_reg_io_ddr    : t_c_mem := (c_mem_reg_rd_latency, 1 , 32 , 1, 'X');
                                                           
   SIGNAL ctlr_dvr_miso         : t_mem_ctlr_miso;
   SIGNAL ctlr_dvr_mosi         : t_mem_ctlr_mosi;
@@ -256,6 +265,11 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_wr_fifo_usedw    : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0);  -- read  side depth of the write FIFO
   SIGNAL ctlr_rd_fifo_usedw    : STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth)-1 DOWNTO 0);  -- write side depth of the read  FIFO
   
+  SIGNAL dp_flush_snk_in       : t_dp_sosi := c_dp_sosi_rst;   
+
+  SIGNAL ctlr_rst_out_i        : STD_LOGIC;
+  SIGNAL mm_reg_io_ddr         : STD_LOGIC_VECTOR(31 DOWNTO 0); 
+  
 BEGIN 
 
   u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
@@ -322,7 +336,7 @@ BEGIN
     src_in         => ctlr_wr_fifo_src_in,
     src_out        => ctlr_wr_fifo_src_out
   );
-  
+ 
   u_dp_flush : ENTITY dp_lib.dp_flush
   GENERIC MAP (
     g_ready_latency => 0,
@@ -402,23 +416,23 @@ BEGIN
 
   u_io_ddr_driver : ENTITY work.io_ddr_driver
   GENERIC MAP (
-    g_tech_ddr         => g_tech_ddr
+    g_tech_ddr => g_tech_ddr
   )
   PORT MAP ( 
-    rst                => ctlr_rst_in,  
-    clk                => ctlr_clk_in,        
+    rst        => ctlr_rst_in,  
+    clk        => ctlr_clk_in,        
 
-    dvr_miso           => ctlr_dvr_miso,
-    dvr_mosi           => ctlr_dvr_mosi,
+    dvr_miso   => ctlr_dvr_miso,
+    dvr_mosi   => ctlr_dvr_mosi,
     
-    wr_snk_in          => ctlr_wr_snk_in, 
-    wr_snk_out         => ctlr_wr_snk_out,
+    wr_snk_in  => ctlr_wr_snk_in, 
+    wr_snk_out => ctlr_wr_snk_out,
     
-    rd_src_out         => ctlr_rd_src_out,
-    rd_src_in          => ctlr_rd_src_in,
+    rd_src_out => ctlr_rd_src_out,
+    rd_src_in  => ctlr_rd_src_in,
 
-    ctlr_miso          => ctlr_miso,
-    ctlr_mosi          => ctlr_mosi
+    ctlr_miso  => ctlr_miso,
+    ctlr_mosi  => ctlr_mosi
   );
   
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
@@ -429,26 +443,56 @@ BEGIN
   )
   PORT MAP (
     -- PLL reference clock
-    ctlr_ref_clk      => ctlr_ref_clk,
-    ctlr_ref_rst      => ctlr_ref_rst,
+    ctlr_ref_clk    => ctlr_ref_clk,
+    ctlr_ref_rst    => ctlr_ref_rst,
 
     -- Controller user interface
-    ctlr_gen_clk      => ctlr_clk_out,
-    ctlr_gen_rst      => ctlr_rst_out,
-    ctlr_gen_clk_2x   => OPEN,
-    ctlr_gen_rst_2x   => OPEN,
+    ctlr_gen_clk    => ctlr_clk_out,
+    ctlr_gen_rst    => ctlr_rst_out_i,
+    ctlr_gen_clk_2x => OPEN,
+    ctlr_gen_rst_2x => OPEN,
 
-    ctlr_mosi         => ctlr_mosi,
-    ctlr_miso         => ctlr_miso,
+    ctlr_mosi       => ctlr_mosi,
+    ctlr_miso       => ctlr_miso,
 
-    term_ctrl_out     => term_ctrl_out,
-    term_ctrl_in      => term_ctrl_in,
+    term_ctrl_out   => term_ctrl_out,
+    term_ctrl_in    => term_ctrl_in,
 
     -- PHY interface
-    phy_in            => phy_in,
-    phy_io            => phy_io,
-    phy_ou            => phy_ou
-  );             
+    phy_in          => phy_in,
+    phy_io          => phy_io,
+    phy_ou          => phy_ou
+  );  
+  
+  ctlr_rst_out  <= ctlr_rst_out_i;
+  mm_reg_io_ddr <= RESIZE_UVEC(ctlr_rst_out_i & ctlr_mosi.flush & ctlr_miso.waitrequest_n & ctlr_miso.done, 32);   
+  
+  u_reg_map : ENTITY common_lib. common_reg_r_w_dc
+  GENERIC MAP (
+    g_cross_clock_domain => TRUE,             -- : BOOLEAN := TRUE;  -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_in_new_latency     => 0,                -- : NATURAL := 0;  -- >= 0
+    g_readback           => FALSE,            -- : BOOLEAN := FALSE;  -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
+    g_reg                => c_mem_reg_io_ddr, -- : t_c_mem := c_mem_reg;
+    g_init_reg           => (OTHERS => '0')   -- : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst      => mm_rst,          --: IN  STD_LOGIC;   -- reset synchronous with mm_clk
+    mm_clk      => mm_clk,          --: IN  STD_LOGIC;   -- memory-mapped bus clock
+    st_rst      => ctlr_rst_in,     --: IN  STD_LOGIC;   -- reset synchronous with st_clk
+    st_clk      => ctlr_clk_in,     --: IN  STD_LOGIC;   -- other clock domain clock
+    
+    -- Memory Mapped Slave in mm_clk domain
+    sla_in      => reg_io_ddr_mosi, --: IN  t_mem_mosi;  -- actual ranges defined by g_reg
+    sla_out     => reg_io_ddr_miso, --: OUT t_mem_miso;  -- actual ranges defined by g_reg
+    
+    -- MM registers in st_clk domain
+    reg_wr_arr  => OPEN,            --  : OUT STD_LOGIC_VECTOR(            g_reg.nof_dat-1 DOWNTO 0);
+    reg_rd_arr  => OPEN,            --  : OUT STD_LOGIC_VECTOR(            g_reg.nof_dat-1 DOWNTO 0);
+    in_new      => '1',             --  : IN  STD_LOGIC := '1';
+    in_reg      => mm_reg_io_ddr,   --  : IN  STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
+    out_reg     => OPEN             --  : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0)
+  );
   
 END str;