Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr =...

Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr = TRUE to get between mm_clk and ctlr_clk_in.

libraries/io/ddr/src/vhdl/mms_io_ddr.vhd

@@ -34,8 +34,6 @@ ENTITY mms_io_ddr IS
     g_sim_model               : BOOLEAN := FALSE;
     g_technology              : NATURAL := c_tech_select_default;
     g_tech_ddr                : t_c_tech_ddr;
-    g_cross_domain_dvr_ctlr   : BOOLEAN := TRUE;
-    g_cross_domain_delay_len  : NATURAL := c_meta_delay_len;
     g_wr_data_w               : NATURAL := 32;  
     g_wr_fifo_depth           : NATURAL := 256;     -- >=16                             , defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K
     g_rd_fifo_depth           : NATURAL := 256;     -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO, default 256 because 32b*256 fits in 1 M9K 
@@ -66,9 +64,6 @@ ENTITY mms_io_ddr IS
     reg_io_ddr_mosi     : IN    t_mem_mosi := c_mem_mosi_rst;  -- register for DDR controller status info
     reg_io_ddr_miso     : OUT   t_mem_miso;
     
-    dvr_clk             : IN    STD_LOGIC;
-    dvr_rst             : IN    STD_LOGIC;
-                        
     -- Write FIFO clock domain
     wr_clk              : IN    STD_LOGIC;
     wr_rst              : IN    STD_LOGIC;
@@ -104,8 +99,8 @@ END mms_io_ddr;
 
 ARCHITECTURE str OF mms_io_ddr IS
 
-  SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
-  SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
+  SIGNAL mm_dvr_miso         : t_mem_ctlr_miso;
+  SIGNAL mm_dvr_mosi         : t_mem_ctlr_mosi;
   
   SIGNAL reg_io_ddr_mosi_arr : t_mem_mosi_arr(1 DOWNTO 0); 
   SIGNAL reg_io_ddr_miso_arr : t_mem_miso_arr(1 DOWNTO 0); 
@@ -130,7 +125,7 @@ BEGIN
     g_sim_model              => g_sim_model,
     g_technology             => g_technology,
     g_tech_ddr               => g_tech_ddr,
-    g_cross_domain_dvr_ctlr  => FALSE, 
+    g_cross_domain_dvr_ctlr  => TRUE,             -- mm_dvr_mosi from io_ddr_reg is in mm_clk domain and needs be crossed to the ctlr_clk_in domain by io_ddr_cross_domain in io_ddr
     g_wr_data_w              => g_wr_data_w,     
     g_wr_fifo_depth          => g_wr_fifo_depth, 
     g_rd_fifo_depth          => g_rd_fifo_depth, 
@@ -161,11 +156,11 @@ BEGIN
     reg_io_ddr_miso => reg_io_ddr_miso_arr(0),
 
     -- Driver clock domain
-    dvr_clk       => dvr_clk,
-    dvr_rst       => dvr_rst,
+    dvr_clk       => mm_clk,
+    dvr_rst       => mm_rst,
     
-    dvr_miso      => ctlr_dvr_miso,
-    dvr_mosi      => ctlr_dvr_mosi,
+    dvr_miso      => mm_dvr_miso,
+    dvr_mosi      => mm_dvr_mosi,
 
     -- Write FIFO clock domain
     wr_clk        => wr_clk,
@@ -201,16 +196,14 @@ BEGIN
     -- Clocks and reset
     mm_rst          => mm_rst,
     mm_clk          => mm_clk, 
-    dp_rst          => dvr_rst,  
-    dp_clk          => dvr_clk,  
     
     -- Memory Mapped Slave in mm_clk domain
     sla_in          => reg_io_ddr_mosi_arr(1),
     sla_out         => reg_io_ddr_miso_arr(1),
     
     -- MM registers in st_clk domain
-    dvr_miso        => ctlr_dvr_miso,
-    dvr_mosi        => ctlr_dvr_mosi
+    dvr_miso        => mm_dvr_miso,
+    dvr_mosi        => mm_dvr_mosi
   );
 
 END str;

libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd

@@ -160,8 +160,6 @@ BEGIN
     g_sim_model               => g_sim_model_ddr,
     g_technology              => g_technology,
     g_tech_ddr                => g_io_tech_ddr,
-    g_cross_domain_dvr_ctlr   => TRUE,  -- cross between mm_clk and ctlr_clk_in
-    g_cross_domain_delay_len  => c_meta_delay_len,
     g_wr_data_w               => g_dp_data_w,
     g_wr_fifo_depth           => c_io_wr_fifo_depth,
     g_rd_fifo_depth           => c_io_rd_fifo_depth,
@@ -192,9 +190,6 @@ BEGIN
     reg_io_ddr_mosi     => reg_io_ddr_mosi,
     reg_io_ddr_miso     => reg_io_ddr_miso,
 
-    dvr_clk             => mm_clk,
-    dvr_rst             => mm_rst,
-
     -- Write FIFO clock domain
     wr_clk              => dp_clk,
     wr_rst              => dp_rst,