Added comment about dvr interface using the t_mem_ctlr_mosi/miso records.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -91,6 +91,14 @@
 --
 --     * = clock domain crossing between dvr_clk and ctlr_clk clock domains.
 --
+--   The dvr interface is mapped also on the t_mem_ctlr_mosi/miso interface:
+--     dvr_miso.done     <= dvr_done;             -- Requested wr or rd sequence is done
+--     dvr_en            <= dvr_mosi.burstbegin;
+--     dvr_wr_not_rd     <= dvr_mosi.wr;          -- No need to use dvr_mosi.rd
+--     dvr_start_address <= dvr_mosi.address(c_ctlr_address_w-1 DOWNTO 0);
+--     dvr_nof_data      <= dvr_mosi.burstsize(c_ctlr_address_w-1 DOWNTO 0);
+--     dvr_wr_flush_en   <= dvr_mosi.flush
+--
 -- Remarks:
 -- . If the dvr_clk=ctlr_clk then the clock domain crossing logic defaults
 --   to wires. However dvr_clk could also be the dp_clk or the mm_clk and then