Pass on ctlr_miso.done to wr_snk_out.xon to support XON flow control.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -172,6 +172,8 @@ BEGIN
   rd_src_out.valid <= ctlr_miso.rdval;
   rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
   
+  wr_snk_out.xon <= ctlr_miso.done;                                  -- xon when controller init is done so ready for access
+  
   p_state : PROCESS(prev_state, state,
                     dvr_en, dvr_wr_not_rd, dvr_start_address, dvr_nof_data,
                     ctlr_miso, wr_snk_in, rd_src_in, 
@@ -186,7 +188,6 @@ BEGIN
     ctlr_mosi.burstbegin   <= burstbegin_evt;                        -- only used for legacy DDR controllers, because the controller can derive it internally by counting wr and rd accesses
     ctlr_mosi.burstsize    <= TO_MEM_CTLR_BURSTSIZE(burst_size);     -- burstsize >= 1,
                                                                      -- no need to hold during burst, because the Avalon constantBurstBehaviour=FALSE (default) of the DDR IP slave
-    wr_snk_out.xon         <= '1';                                   -- xon is fixed '1'
     wr_snk_out.ready       <= '0';
     nxt_dvr_done           <= '0';
     nxt_cur_address        <= cur_address;