Commits · a0e87e618106d762d06ebc53ca352e3dbd892439 · RTSD / HDL · GitLab

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May 20, 2015
- Updated all IP related files to match Quartus 15.0 which uses libraries with... · 6237fca5
  Eric Kooistra authored 10 years ago
  6237fca5
May 06, 2015
- -Added fast behavioural model to tech_ddr.vhd; · cb21fc96
  Daniel van der Schuur authored 10 years ago
  cb21fc96
May 01, 2015
- ip_stratixiv_ddr3_mem_model only for simulation · 13681134
  Kenneth Hiemstra authored 10 years ago
  
  13681134
Apr 29, 2015
- Fixed connections to single rank memory · ade1b60b
  Zanting authored 10 years ago
  
  ade1b60b
Apr 24, 2015
- Updated c_tech_ddr3_max · a4f69684
  Zanting authored 10 years ago
  
  a4f69684
Apr 22, 2015
- Added DDR3 single rank master and slave · 1188f0b9
  Zanting authored 10 years ago
  
  1188f0b9
- Added DDR3 single rank master and slave · 0b1592e6
  Zanting authored 10 years ago
  
  0b1592e6
Apr 17, 2015
- Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg · 7053afa9
  Eric Kooistra authored 10 years ago
  
  7053afa9
Apr 08, 2015
- connected cal_ok and fail · d55d0ad2
  Pepping authored 10 years ago
  
  d55d0ad2
- Added array types · 1fcaa2e3
  Pepping authored 10 years ago
  
  1fcaa2e3
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 8e1a6162
  Eric Kooistra authored 10 years ago
  8e1a6162
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · 7095b485
  Eric Kooistra authored 10 years ago
  7095b485
- Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed... · d51f8638
  Eric Kooistra authored 10 years ago
  d51f8638
- Rename ctlr_ref_clk into ref_clk to have simpler and more clear name. · f1cda4e0
  Eric Kooistra authored 10 years ago
  
  f1cda4e0
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 80ba2261
  Eric Kooistra authored 10 years ago
  
  80ba2261
- Updated description of g_sim. · fc437369
  Eric Kooistra authored 10 years ago
  
  fc437369
Mar 17, 2015
- new key in use 'hdl_lib_excludes' · d8b4fb72
  Kenneth Hiemstra authored 10 years ago
  
  d8b4fb72
Mar 11, 2015
- splitted the terminationcontrol lines from the record types... · ed82dce7
  Kenneth Hiemstra authored 10 years ago
  ed82dce7
Feb 20, 2015
- Added g_sim because memory model should not be included in the synthesis · b02115b8
  Zanting authored 10 years ago
  
  b02115b8
Feb 13, 2015
- Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key... · ee68785f
  Eric Kooistra authored 10 years ago
  ee68785f
Feb 05, 2015
- svn added missing file. · 6a945baf
  Eric Kooistra authored 10 years ago
  
  6a945baf
Jan 22, 2015
- Define command_queue_depth=16 in c_tech_ddr_max. · fa92406f
  Eric Kooistra authored 10 years ago
  
  fa92406f
Jan 20, 2015
- Added ip_arria10 DDR4 IP for 4Gbyte, 1600 MTps. · 0c910766
  Eric Kooistra authored 10 years ago
  
  0c910766
- Added 4GByte DDR4 memory model for 1600 Mtransfers/s. · 30bdacdd
  Eric Kooistra authored 10 years ago
  
  30bdacdd
- Added ip_arria10 DDR4 IP and mem_model.diff · f422be4e
  Eric Kooistra authored 10 years ago
  
  f422be4e
Jan 08, 2015
- Support internal DDR memory model for simulation in tech_ddr. · 6a3d5a63
  Eric Kooistra authored 10 years ago
  
  6a3d5a63
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- Added c_tech_ddr_phy_*_x constants. · 945c7d3b
  Eric Kooistra authored 10 years ago
  
  945c7d3b
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Clarified ctlr_init_done. · c576df23
  Eric Kooistra authored 10 years ago
  
  c576df23
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  b559785d
Jan 06, 2015
- No need for c_dq_address_w argument in func_tech_ddr_dq_address(). · 19926973
  Eric Kooistra authored 10 years ago
  
  19926973
- set MEM_TRCD=6 to avoid timing error message in simulation. · 34014215
  Eric Kooistra authored 10 years ago
  
  34014215
Jan 05, 2015
- Rename ctrl into ctlr. · d61c490e
  Eric Kooistra authored 10 years ago
  
  d61c490e
Dec 22, 2014
- Rename ctrl into ctlr. · 8d6b8949
  Eric Kooistra authored 10 years ago
  
  8d6b8949
- Added functions for resizing to the mosi/miso record slv fields. · 4cc7a033
  Eric Kooistra authored 10 years ago
  
  4cc7a033
- Added func_tech_ddr_dq_address() and func_tech_ddr_ctrl_address(). · b28b7e1c
  Eric Kooistra authored 10 years ago
  
  b28b7e1c
- Defined c_tech_ddr_miso_rst and c_tech_ddr_mosi_rst. · 08752f82
  Eric Kooistra authored 10 years ago
  
  08752f82
- Corrected dqs_n connection. · 64542894
  Eric Kooistra authored 10 years ago
  
  64542894
Dec 19, 2014
- Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixivdiff · 7c4c80d1
  Eric Kooistra authored 10 years ago
  
  7c4c80d1