Added ip_arria10 DDR4 IP and mem_model.diff

libraries/technology/ddr/hdllib.cfg

 hdl_lib_name = tech_ddr
 hdl_library_clause_name = tech_ddr_lib
-hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_mem_model common
+hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master
+               ip_stratixiv_ddr3_uphy_4g_800_slave
+               ip_stratixiv_ddr3_mem_model
+               ip_arria10_ddr4_4g_1600
+               ip_arria10_ddr4_8g_2400
+               ip_arria10_ddr4_mem_model_141
+               common
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR
@@ -10,6 +16,7 @@ synth_files =
     tech_ddr_pkg.vhd
     tech_ddr_component_pkg.vhd
     tech_ddr_stratixiv.vhd
+    tech_ddr_arria10.vhd
     
     tech_ddr_mem_model_component_pkg.vhd
     tech_ddr_mem_model.vhd