Corrected dqs_n connection.

libraries/technology/ddr/tech_ddr_mem_model.vhd

@@ -95,7 +95,7 @@ BEGIN
       mem_dm      => mem_in.dm(g_tech_ddr.dqs_w-1 DOWNTO 0),     -- MEM_IF_DQS_WIDTH
       mem_dq      => mem_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0),      -- MEM_IF_DQ_WIDTH
       mem_dqs     => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0),    -- MEM_IF_DQS_WIDTH
-      mem_dqs_n   => mem_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0),    -- MEM_IF_DQS_WIDTH
+      mem_dqs_n   => mem_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0),  -- MEM_IF_DQS_WIDTH
       mem_odt     => mem_in.odt(g_tech_ddr.odt_w-1 DOWNTO 0)     -- MEM_IF_ODT_WIDTH
     );
   END GENERATE;