No need for c_dq_address_w argument in func_tech_ddr_dq_address().

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -113,21 +113,17 @@ PACKAGE tech_ddr_pkg IS
     row       : STD_LOGIC_VECTOR(c_tech_ddr_max.a_row_w-1 DOWNTO 0); 
     col       : STD_LOGIC_VECTOR(c_tech_ddr_max.a_col_w-1 DOWNTO 0);
   END RECORD;
-
+  
   TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr; 
   
   CONSTANT c_tech_ddr_addr_lo     : t_tech_ddr_addr := ((OTHERS=>'0'),
                                                         (OTHERS=>'0'),
                                                         (OTHERS=>'0'),
                                                         (OTHERS=>'0'));
-  CONSTANT c_tech_ddr_addr_hi_4gb : t_tech_ddr_addr := ((OTHERS=>'1'),
-                                                        (OTHERS=>'1'),
-                                                        (OTHERS=>'1'),
-                                                        TO_UVEC(2**c_tech_ddr_4g.a_col_w-c_tech_ddr_4g.rsl, c_tech_ddr_max.a_col_w));
 
-  FUNCTION func_tech_ddr_dq_address(  dq_address : STD_LOGIC_VECTOR; g_tech_ddr : t_c_tech_ddr                            ) RETURN t_tech_ddr_addr;
-  FUNCTION func_tech_ddr_dq_address(  ddr_addr   : t_tech_ddr_addr;  g_tech_ddr : t_c_tech_ddr; c_dq_address_w   : NATURAL) RETURN STD_LOGIC_VECTOR;
-  FUNCTION func_tech_ddr_ctlr_address(ddr_addr   : t_tech_ddr_addr;  g_tech_ddr : t_c_tech_ddr; c_ctlr_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
+  FUNCTION func_tech_ddr_dq_address(  dq_address : STD_LOGIC_VECTOR; c_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr;
+  FUNCTION func_tech_ddr_dq_address(  ddr_addr   : t_tech_ddr_addr;  c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR;
+  FUNCTION func_tech_ddr_ctlr_address(ddr_addr   : t_tech_ddr_addr;  c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR;
   
   -- PHY MM access signal record
   
@@ -194,29 +190,31 @@ PACKAGE BODY tech_ddr_pkg IS
     RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
   END;
   
-  FUNCTION func_tech_ddr_dq_address(dq_address : STD_LOGIC_VECTOR; g_tech_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr IS
+  FUNCTION func_tech_ddr_dq_address(dq_address : STD_LOGIC_VECTOR; c_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr IS
     VARIABLE v_ddr_addr : t_tech_ddr_addr := c_tech_ddr_addr_lo;
   BEGIN
-    v_ddr_addr.chip(g_tech_ddr.cs_w_w -1 DOWNTO 0) := dq_address(g_tech_ddr.cs_w_w+g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w); 
-    v_ddr_addr.bank(g_tech_ddr.ba_w   -1 DOWNTO 0) := dq_address(                  g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO                 g_tech_ddr.a_w+g_tech_ddr.a_col_w);
-    v_ddr_addr.row( g_tech_ddr.a_w    -1 DOWNTO 0) := dq_address(                                  g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO                                g_tech_ddr.a_col_w);
-    v_ddr_addr.col( g_tech_ddr.a_col_w-1 DOWNTO 0) := dq_address(                                                 g_tech_ddr.a_col_w-1 DOWNTO                                                 0);
+    v_ddr_addr.chip(c_ddr.cs_w_w -1 DOWNTO 0) := dq_address(c_ddr.cs_w_w+c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w); 
+    v_ddr_addr.bank(c_ddr.ba_w   -1 DOWNTO 0) := dq_address(             c_ddr.ba_w+c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO            c_ddr.a_w+c_ddr.a_col_w);
+    v_ddr_addr.row( c_ddr.a_w    -1 DOWNTO 0) := dq_address(                        c_ddr.a_w+c_ddr.a_col_w-1 DOWNTO                      c_ddr.a_col_w);
+    v_ddr_addr.col( c_ddr.a_col_w-1 DOWNTO 0) := dq_address(                                  c_ddr.a_col_w-1 DOWNTO                                  0);
     RETURN v_ddr_addr;
   END;
     
-  FUNCTION func_tech_ddr_dq_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_dq_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
+  FUNCTION func_tech_ddr_dq_address(ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR IS
+    CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(c_ddr);
   BEGIN
-    RETURN RESIZE_UVEC(ddr_addr.chip(g_tech_ddr.cs_w_w -1 DOWNTO 0) &
-                       ddr_addr.bank(g_tech_ddr.ba_w   -1 DOWNTO 0) &
-                       ddr_addr.row( g_tech_ddr.a_row_w-1 DOWNTO 0) &
-                       ddr_addr.col( g_tech_ddr.a_col_w-1 DOWNTO 0), c_dq_address_w);
+    RETURN RESIZE_UVEC(ddr_addr.chip(c_ddr.cs_w_w -1 DOWNTO 0) &
+                       ddr_addr.bank(c_ddr.ba_w   -1 DOWNTO 0) &
+                       ddr_addr.row( c_ddr.a_row_w-1 DOWNTO 0) &
+                       ddr_addr.col( c_ddr.a_col_w-1 DOWNTO 0), c_dq_address_w);
   END;
   
-  FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctlr_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
-    CONSTANT c_dq_address_w : NATURAL                                     := func_tech_ddr_dq_address_w(g_tech_ddr);
-    CONSTANT c_dq_address   : STD_LOGIC_VECTOR(c_dq_address_w-1 DOWNTO 0) := func_tech_ddr_dq_address(ddr_addr, g_tech_ddr, c_dq_address_w);
+  FUNCTION func_tech_ddr_ctlr_address(ddr_addr : t_tech_ddr_addr; c_ddr : t_c_tech_ddr) RETURN STD_LOGIC_VECTOR IS
+    CONSTANT c_dq_address_w   : NATURAL                                     := func_tech_ddr_dq_address_w(c_ddr);
+    CONSTANT c_dq_address     : STD_LOGIC_VECTOR(c_dq_address_w-1 DOWNTO 0) := func_tech_ddr_dq_address(ddr_addr, c_ddr);
+    CONSTANT c_ctlr_address_w : NATURAL                                     := func_tech_ddr_ctlr_address_w(c_ddr);
   BEGIN
-    RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO g_tech_ddr.rsl_w), c_ctlr_address_w);
+    RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO c_ddr.rsl_w), c_ctlr_address_w);
   END;
   
   FUNCTION TO_DDR_CTLR_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS