Added g_sim because memory model should not be included in the synthesis

libraries/technology/ddr/tech_ddr.vhd

@@ -95,6 +95,7 @@ BEGIN
   gen_sim: IF g_sim=TRUE GENERATE
     u_tech_ddr_memory_model : ENTITY work.tech_ddr_memory_model
     GENERIC MAP (
+      g_sim => g_sim,
       g_tech_ddr => g_tech_ddr
     )
     PORT MAP (

libraries/technology/ddr/tech_ddr_mem_model.vhd

@@ -38,6 +38,7 @@ USE work.tech_ddr_mem_model_component_pkg.ALL;
 
 ENTITY tech_ddr_memory_model IS
   GENERIC (
+    g_sim        : BOOLEAN := FALSE; --FALSE: use real memory; TRUE: use generated memory
     g_tech_ddr   : t_c_tech_ddr
   );
   PORT (
@@ -58,7 +59,7 @@ ARCHITECTURE str OF tech_ddr_memory_model IS
   
 BEGIN
 
-  gen_ip_stratixiv_ddr_memory_model : IF g_tech_ddr.name="DDR3" GENERATE
+  gen_ip_stratixiv_ddr_memory_model : IF g_sim = TRUE AND g_tech_ddr.name="DDR3" GENERATE
     u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
     GENERIC MAP (
       MEM_IF_CLK_EN_WIDTH          => g_tech_ddr.cke_w,
@@ -106,7 +107,7 @@ BEGIN
     );
   END GENERATE;
   
-  gen_ip_arria10_ddr_memory_model : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 GENERATE
+  gen_ip_arria10_ddr_memory_model : IF g_sim = TRUE AND g_tech_ddr.name="DDR4" AND c_gigabytes=4 GENERATE
     u_ip_arria10_ddr_memory_model : ed_sim_altera_emif_mem_model_141_z3tvrmq
     PORT MAP (
       mem_ck       => mem_in.ck(g_tech_ddr.ck_w-1 DOWNTO 0),      -- mem_conduit_end.mem_ck