set MEM_TRCD=6 to avoid timing error message in simulation.

libraries/technology/ddr/tech_ddr_mem_model.vhd

@@ -71,7 +71,7 @@ BEGIN
       MEM_IF_DQ_WIDTH              => g_tech_ddr.dq_w,
       MEM_MIRROR_ADDRESSING_DEC    => 0,
       MEM_TRTP                     => 8,
-      MEM_TRCD                     => 8,
+      MEM_TRCD                     => 6,
       MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
       MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
       MEM_REGDIMM_ENABLED          => 0,