Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixivdiff

libraries/technology/ddr/hdllib.cfg

 hdl_lib_name = tech_ddr
 hdl_library_clause_name = tech_ddr_lib
-hdl_lib_uses = common
+hdl_lib_uses = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave ip_stratixiv_ddr3_mem_model common
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR
@@ -13,3 +13,5 @@ synth_files =
     tech_ddr.vhd
 
 test_bench_files =
+    tech_ddr_mem_model_component_pkg.vhd
+    tech_ddr_mem_model.vhd