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Commit ade1b60b authored by Zanting's avatar Zanting
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Fixed connections to single rank memory

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libraries/technology/ddr/tech_ddr_component_pkg.vhd
+ 6
− 6
View file @ ade1b60b
...@@ -147,8 +147,8 @@ PACKAGE tech_ddr_component_pkg IS ...@@ -147,8 +147,8 @@ PACKAGE tech_ddr_component_pkg IS
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cke mem_cke : OUT STD_LOGIC; -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cs_n mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
...@@ -157,7 +157,7 @@ PACKAGE tech_ddr_component_pkg IS ...@@ -157,7 +157,7 @@ PACKAGE tech_ddr_component_pkg IS
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_odt mem_odt : OUT STD_LOGIC; -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
...@@ -200,8 +200,8 @@ PACKAGE tech_ddr_component_pkg IS ...@@ -200,8 +200,8 @@ PACKAGE tech_ddr_component_pkg IS
mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba mem_ba : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- .mem_ba
mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck mem_ck : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck
mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n mem_ck_n : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- .mem_ck_n
mem_cke : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cke mem_cke : OUT STD_LOGIC; -- .mem_cke
mem_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_cs_n mem_cs_n : OUT STD_LOGIC; -- .mem_cs_n
mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm mem_dm : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dm
mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n mem_ras_n : OUT STD_LOGIC; -- .mem_ras_n
mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n mem_cas_n : OUT STD_LOGIC; -- .mem_cas_n
...@@ -210,7 +210,7 @@ PACKAGE tech_ddr_component_pkg IS ...@@ -210,7 +210,7 @@ PACKAGE tech_ddr_component_pkg IS
mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq mem_dq : INOUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- .mem_dq
mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs mem_dqs : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs
mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n mem_dqs_n : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- .mem_dqs_n
mem_odt : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- .mem_odt mem_odt : OUT STD_LOGIC; -- .mem_odt
avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n avl_ready : OUT STD_LOGIC; -- avl.waitrequest_n
avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer avl_burstbegin : IN STD_LOGIC; -- .beginbursttransfer
avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address avl_addr : IN STD_LOGIC_VECTOR(26 DOWNTO 0); -- .address
......
libraries/technology/ddr/tech_ddr_stratixiv.vhd
+ 21
− 7
View file @ ade1b60b
...@@ -86,10 +86,14 @@ ARCHITECTURE str OF tech_ddr_stratixiv IS ...@@ -86,10 +86,14 @@ ARCHITECTURE str OF tech_ddr_stratixiv IS
SIGNAL i_ctlr_gen_rst : STD_LOGIC; SIGNAL i_ctlr_gen_rst : STD_LOGIC;
SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC; SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
SIGNAL i_mem_cke : STD_LOGIC;
SIGNAL i_mem_cs_n : STD_LOGIC;
SIGNAL i_mem_odt : STD_LOGIC;
BEGIN BEGIN
ref_rst_n <= NOT ref_rst; ref_rst_n <= NOT ref_rst;
gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE AND g_tech_ddr.rank="DUAL " GENERATE gen_ip_stratixiv_ddr3_uphy_4g_800_master : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=TRUE AND g_tech_ddr.rank="DUAL " GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP ( PORT MAP (
...@@ -205,8 +209,8 @@ BEGIN ...@@ -205,8 +209,8 @@ BEGIN
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke mem_cke => i_mem_cke, -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n mem_cs_n => i_mem_cs_n, -- .mem_cs_n
mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
mem_ras_n => phy_ou.ras_n, -- .mem_ras_n mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
mem_cas_n => phy_ou.cas_n, -- .mem_cas_n mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
...@@ -215,7 +219,7 @@ BEGIN ...@@ -215,7 +219,7 @@ BEGIN
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt mem_odt => i_mem_odt, -- .mem_odt
avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
...@@ -242,6 +246,11 @@ BEGIN ...@@ -242,6 +246,11 @@ BEGIN
pll_config_clk => OPEN, -- .pll_config_clk pll_config_clk => OPEN, -- .pll_config_clk
dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
); );
phy_ou.cke(0) <= i_mem_cke;
phy_ou.cs_n(0) <= i_mem_cs_n;
phy_ou.odt(0) <= i_mem_odt;
END GENERATE; END GENERATE;
gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE AND g_tech_ddr.rank="SINGLE" GENERATE gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : IF g_tech_ddr.name="DDR3" AND c_gigabytes=4 AND g_tech_ddr.mts=800 AND g_tech_ddr.master=FALSE AND g_tech_ddr.rank="SINGLE" GENERATE
...@@ -257,8 +266,8 @@ BEGIN ...@@ -257,8 +266,8 @@ BEGIN
mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba mem_ba => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck mem_ck => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck
mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n mem_ck_n => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0), -- .mem_ck_n
mem_cke => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0), -- .mem_cke mem_cke => i_mem_cke, -- .mem_cke
mem_cs_n => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n mem_cs_n => i_mem_cs_n, -- .mem_cs_n
mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm mem_dm => phy_ou.dm(g_tech_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
mem_ras_n => phy_ou.ras_n, -- .mem_ras_n mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
mem_cas_n => phy_ou.cas_n, -- .mem_cas_n mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
...@@ -267,7 +276,7 @@ BEGIN ...@@ -267,7 +276,7 @@ BEGIN
mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq mem_dq => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs mem_dqs => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n mem_dqs_n => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
mem_odt => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0), -- .mem_odt mem_odt => i_mem_odt, -- .mem_odt
avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n avl_ready => ctlr_miso.waitrequest_n, -- avl.waitrequest_n
avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer avl_burstbegin => ctlr_mosi.burstbegin, -- .beginbursttransfer
avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address avl_addr => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0), -- .address
...@@ -292,6 +301,11 @@ BEGIN ...@@ -292,6 +301,11 @@ BEGIN
pll_config_clk => OPEN, -- .pll_config_clk pll_config_clk => OPEN, -- .pll_config_clk
dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
); );
phy_ou.cke(0) <= i_mem_cke;
phy_ou.cs_n(0) <= i_mem_cs_n;
phy_ou.odt(0) <= i_mem_odt;
END GENERATE; END GENERATE;
i_ctlr_gen_rst <= NOT ctlr_gen_rst_n; i_ctlr_gen_rst <= NOT ctlr_gen_rst_n;
......
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