Commits · 6f61c32677b0e8bc381f25d03b7c9f93b2bf8f14 · RTSD / HDL · GitLab

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Jul 09, 2015
- Pass on ctlr_miso.done to wr_snk_out.xon to support XON flow control. · d48977ca
  Eric Kooistra authored 9 years ago
  
  d48977ca
Jun 26, 2015
- Use separate g_dp_wr_fifo_depth and g_dp_rd_fifo_depth. · fbadd894
  Eric Kooistra authored 9 years ago
  
  fbadd894
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored 9 years ago
  
  12fd53ea
Jun 25, 2015
- Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr =... · 755f1acb
  Eric Kooistra authored 9 years ago
  755f1acb
- Used g_cross_domain_delay_len=c_meta_delay_len fixed instead of via generic. · a8775752
  Eric Kooistra authored 9 years ago
  
  a8775752
- Removed clock domain crossing logic for this control register, because that is... · edb2c90e
  Eric Kooistra authored 9 years ago
  edb2c90e
Jun 24, 2015
- Register ctlr_wr_flush_en to ease timing closure. · df1c1e28
  Eric Kooistra authored 9 years ago
  
  df1c1e28
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored 9 years ago
  
  33e83b5a
- Added g_sim_model. Renamed instances. · 0306fe4b
  Eric Kooistra authored 9 years ago
  
  0306fe4b
- Provide streaming access to IO_DDR using a Tx seq and a Rx seq with optional DB RAM. · 61f16974
  Eric Kooistra authored 9 years ago
  
  61f16974
Jun 11, 2015
- Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and... · 4e1d928d
  Eric Kooistra authored 9 years ago
  4e1d928d
May 08, 2015
- Corrected asserting ctlr_mosi.burstbegin for only one clock cycle as specified... · bd490884
  Eric Kooistra authored 10 years ago
  bd490884
- Corrected use of ctrl_miso.waitrequest_n to avoid combinational loop with ctrl_mosi.wr and rd. · 5551601d
  Eric Kooistra authored 10 years ago
  
  5551601d
May 06, 2015
- -Added fast behavioural model to tech_ddr.vhd; · cb21fc96
  Daniel van der Schuur authored 10 years ago
  cb21fc96
Apr 23, 2015
- Initial commit · 6aeae2e5
  Pepping authored 10 years ago
  
  6aeae2e5
Apr 15, 2015
- Fixed default value of wr_snk_out.xon to '1'. This fixes the DDR3 issue on hardware. · 4c5369bf
  Zanting authored 10 years ago
  
  4c5369bf
Apr 13, 2015
- Added more signals to register · e3bf0da1
  Pepping authored 10 years ago
  
  e3bf0da1
Apr 10, 2015
- Use default reg_io_ddr_mosi input value to allow not connecting it. · 7b7329ca
  Eric Kooistra authored 10 years ago
  
  7b7329ca
Apr 09, 2015
- - Added fifo used words to the register for both rd and wr fifo · 996114aa
  Pepping authored 10 years ago
  996114aa
Apr 08, 2015
- Added cal_fail and cal_ok to register · f1fd048b
  Pepping authored 10 years ago
  
  f1fd048b
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 17ede428
  Eric Kooistra authored 10 years ago
  17ede428
- Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more... · fe14a691
  Eric Kooistra authored 10 years ago
  fe14a691
Mar 30, 2015
- Added register map for io_ddr ctrol signals. · 2578f0bd
  Pepping authored 10 years ago
  
  2578f0bd
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 24cd1054
  Eric Kooistra authored 10 years ago
  
  24cd1054
Mar 11, 2015
- splitted the terminationcontrol lines from the record types... · f7b6f80d
  Kenneth Hiemstra authored 10 years ago
  f7b6f80d
Jan 23, 2015
- Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst... · 3ac8fbe4
  Eric Kooistra authored 10 years ago
  3ac8fbe4
- Cosmetic. · 8ff6fba0
  Eric Kooistra authored 10 years ago
  
  8ff6fba0
- Default ctlr_mosi.burstsize <= burst_size fits all states. · 9a6c734a
  Eric Kooistra authored 10 years ago
  
  9a6c734a
Jan 22, 2015
- Added comments regarding the command queue deptand the constantBurstBehaviour. · 4a7e810d
  Eric Kooistra authored 10 years ago
  
  4a7e810d
Jan 20, 2015
- Pass on g_delay_len => g_cross_domain_delay_len. · 5c62b3e8
  Eric Kooistra authored 10 years ago
  
  5c62b3e8
- Added address_cnt_is_0 register to easytiming closure. · 34f0ad34
  Eric Kooistra authored 10 years ago
  
  34f0ad34
Jan 12, 2015
- Added comments of need for write and read FIFO. Added comments on flushing the write FIFO. · ae2cdecf
  Eric Kooistra authored 10 years ago
  
  ae2cdecf
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- cosmetic. · 1be7ce19
  Eric Kooistra authored 10 years ago
  
  1be7ce19
- Improved comments. · c737eec8
  Eric Kooistra authored 10 years ago
  
  c737eec8
- Only need to reset the state reg, do not reset the other signals to easy... · 6ca43322
  Eric Kooistra authored 10 years ago
  6ca43322
- Added comment about dvr interface using the t_mem_ctlr_mosi/miso records. · 29cf2fb3
  Eric Kooistra authored 10 years ago
  
  29cf2fb3
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Wire dvr_done via new dvr_miso.done field instead of via the dvr_miso.waitrequest_n field. · 471d01b1
  Eric Kooistra authored 10 years ago
  
  471d01b1
- Connect dvr_wr_flush_en via dvr_mosi.flush. · 5e468fd4
  Eric Kooistra authored 10 years ago
  
  5e468fd4