Commits · 6aeae2e54ec4bda7cef0b1cf63151ea9f0784dc0 · RTSD / HDL · GitLab

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Apr 23, 2015
- Initial commit · 6aeae2e5
  Pepping authored 10 years ago
  
  6aeae2e5
Apr 15, 2015
- Fixed default value of wr_snk_out.xon to '1'. This fixes the DDR3 issue on hardware. · 4c5369bf
  Zanting authored 10 years ago
  
  4c5369bf
Apr 13, 2015
- Added more signals to register · e3bf0da1
  Pepping authored 10 years ago
  
  e3bf0da1
Apr 10, 2015
- Use default reg_io_ddr_mosi input value to allow not connecting it. · 7b7329ca
  Eric Kooistra authored 10 years ago
  
  7b7329ca
Apr 09, 2015
- - Added fifo used words to the register for both rd and wr fifo · 996114aa
  Pepping authored 10 years ago
  996114aa
Apr 08, 2015
- Added cal_fail and cal_ok to register · f1fd048b
  Pepping authored 10 years ago
  
  f1fd048b
- Removed internal DDR memory model (now needs to be instantiated in tb). Use... · 17ede428
  Eric Kooistra authored 10 years ago
  17ede428
- Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more... · fe14a691
  Eric Kooistra authored 10 years ago
  fe14a691
Mar 30, 2015
- Added register map for io_ddr ctrol signals. · 2578f0bd
  Pepping authored 10 years ago
  
  2578f0bd
Mar 25, 2015
- Renamed g_sim into g_use_ddr_memory_model. · 24cd1054
  Eric Kooistra authored 10 years ago
  
  24cd1054
Mar 11, 2015
- splitted the terminationcontrol lines from the record types... · f7b6f80d
  Kenneth Hiemstra authored 10 years ago
  f7b6f80d
Jan 23, 2015
- Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst... · 3ac8fbe4
  Eric Kooistra authored 10 years ago
  3ac8fbe4
- Cosmetic. · 8ff6fba0
  Eric Kooistra authored 10 years ago
  
  8ff6fba0
- Default ctlr_mosi.burstsize <= burst_size fits all states. · 9a6c734a
  Eric Kooistra authored 10 years ago
  
  9a6c734a
Jan 22, 2015
- Added comments regarding the command queue deptand the constantBurstBehaviour. · 4a7e810d
  Eric Kooistra authored 10 years ago
  
  4a7e810d
Jan 20, 2015
- Pass on g_delay_len => g_cross_domain_delay_len. · 5c62b3e8
  Eric Kooistra authored 10 years ago
  
  5c62b3e8
- Added address_cnt_is_0 register to easytiming closure. · 34f0ad34
  Eric Kooistra authored 10 years ago
  
  34f0ad34
Jan 12, 2015
- Added comments of need for write and read FIFO. Added comments on flushing the write FIFO. · ae2cdecf
  Eric Kooistra authored 10 years ago
  
  ae2cdecf
Jan 08, 2015
- Added g_sim, when TRUE then use internal DDR memory model in tech_ddr... · e8956d9d
  Eric Kooistra authored 10 years ago
  e8956d9d
- cosmetic. · 1be7ce19
  Eric Kooistra authored 10 years ago
  
  1be7ce19
- Improved comments. · c737eec8
  Eric Kooistra authored 10 years ago
  
  c737eec8
- Only need to reset the state reg, do not reset the other signals to easy... · 6ca43322
  Eric Kooistra authored 10 years ago
  6ca43322
- Added comment about dvr interface using the t_mem_ctlr_mosi/miso records. · 29cf2fb3
  Eric Kooistra authored 10 years ago
  
  29cf2fb3
- Pass on local_init_done from IP via ctlr_miso.done instead of via separate signal ctlr_init_done. · 37b92e7f
  Eric Kooistra authored 10 years ago
  
  37b92e7f
- Wire dvr_done via new dvr_miso.done field instead of via the dvr_miso.waitrequest_n field. · 471d01b1
  Eric Kooistra authored 10 years ago
  
  471d01b1
- Connect dvr_wr_flush_en via dvr_mosi.flush. · 5e468fd4
  Eric Kooistra authored 10 years ago
  
  5e468fd4
- Map original dvr interface signals to dvr_mosi/miso of the record type t_mem_ctlr_mosi/miso. · de3b07b2
  Eric Kooistra authored 10 years ago
  
  de3b07b2
- Added comment to clarify which are the input and output ports. · ae7d3eab
  Eric Kooistra authored 10 years ago
  
  ae7d3eab
- Define g_delay_len : NATURAL := c_meta_delay_len. · afe300d0
  Eric Kooistra authored 10 years ago
  
  afe300d0
- Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the... · b559785d
  Eric Kooistra authored 10 years ago
  b559785d
- No need to use wr_fifo_usedw, because snk_in.valid does not need to remain active during the burst. · 1cace676
  Eric Kooistra authored 10 years ago
  
  1cace676
- Clarified flushing mixed width FIFO. · c2e7f0e8
  Eric Kooistra authored 10 years ago
  
  c2e7f0e8
Jan 07, 2015
- Replaced dvr_end_address by dvr_nof_data. · f77d17f5
  Eric Kooistra authored 10 years ago
  
  f77d17f5
Jan 06, 2015
- Use address_cnt instead of diff_address and addresses_rem. · a620209c
  Eric Kooistra authored 10 years ago
  
  a620209c
- Renamed req_burst_cycles into burst_wr_cnt. · 66540bfd
  Eric Kooistra authored 10 years ago
  
  66540bfd
- Rename dvr_start_addr into dvr_start_address. · aa967f59
  Eric Kooistra authored 10 years ago
  
  aa967f59
- Use ctlr slv address instead of record address. · f9b1a01f
  Eric Kooistra authored 10 years ago
  
  f9b1a01f
- Use ctlr slv address instead of record address. Separate p_burst_size into wr... · c873aa5c
  Eric Kooistra authored 10 years ago
  c873aa5c
- Change dvr_wr_fifo_usedw into more appropriate wr_fifo_usedw in wr_clk domain. · cb48c6e0
  Eric Kooistra authored 10 years ago
  
  cb48c6e0
Jan 05, 2015
- Removed ctrl_rdy. Instead better use dvr_done to monitor the DDR state via a MM register if needed. · ac1d2c4c
  Eric Kooistra authored 10 years ago
  
  ac1d2c4c