Removed ctrl_rdy. Instead better use dvr_done to monitor the DDR state via a MM register if needed.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -127,8 +127,6 @@ ENTITY io_ddr IS
     ctlr_clk_in        : IN    STD_LOGIC;  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        : IN    STD_LOGIC;  -- connect ctlr_rst_out to ctlr_rst_in at top level
     
-    ctlr_rdy           : OUT   STD_LOGIC;
-
     -- Driver clock domain
     dvr_clk            : IN    STD_LOGIC;
     dvr_rst            : IN    STD_LOGIC;
@@ -207,8 +205,6 @@ ARCHITECTURE str OF io_ddr IS
   
 BEGIN 
 
-  ctlr_rdy <= ctlr_miso.waitrequest_n;
-  
   u_io_ddr_cross_domain : ENTITY work.io_ddr_cross_domain
   GENERIC MAP (
     g_cross_domain => g_cross_domain_dvr_ctlr

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -97,8 +97,6 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dp_clk               : STD_LOGIC := '0';
   SIGNAL dp_rst               : STD_LOGIC;
 
-  SIGNAL ctlr_rdy             : STD_LOGIC;
-
   SIGNAL dvr_start_addr       : t_tech_ddr_addr; 
   SIGNAL dvr_end_addr         : t_tech_ddr_addr;
 
@@ -286,8 +284,6 @@ BEGIN
     ctlr_clk_in        => ctlr_clk,  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        => ctlr_rst,
     
-    ctlr_rdy           => ctlr_rdy,
-
     -- Driver clock domain
     dvr_clk            => dvr_clk,
     dvr_rst            => dvr_rst,