Use ctlr slv address instead of record address.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -131,8 +131,8 @@ ENTITY io_ddr IS
     dvr_en             : IN    STD_LOGIC;
     dvr_done           : OUT   STD_LOGIC;
     dvr_wr_not_rd      : IN    STD_LOGIC;
-    dvr_start_addr     : IN    t_tech_ddr_addr;
-    dvr_end_addr       : IN    t_tech_ddr_addr;
+    dvr_start_addr     : IN    STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
+    dvr_end_addr       : IN    STD_LOGIC_VECTOR(func_tech_ddr_ctlr_address_w(g_tech_ddr)-1 DOWNTO 0);
     dvr_wr_flush_en    : IN    STD_LOGIC := '0';
 
     -- Write FIFO clock domain
@@ -165,6 +165,7 @@ ARCHITECTURE str OF io_ddr IS
   CONSTANT c_wr_use_ctrl       : BOOLEAN := sel_a_b(g_wr_flush_mode="SOP", TRUE, FALSE);
   CONSTANT c_wr_fifo_use_ctrl  : BOOLEAN := c_wr_use_sync OR c_wr_use_ctrl;
   
+  CONSTANT c_ctlr_address_w    : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
   CONSTANT c_ctlr_data_w       : NATURAL := func_tech_ddr_ctlr_data_w(g_tech_ddr);
   CONSTANT c_wr_fifo_depth     : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w);  -- get FIFO depth at write side
   
@@ -174,8 +175,8 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_dvr_en           : STD_LOGIC;
   SIGNAL ctlr_dvr_done         : STD_LOGIC;
   SIGNAL ctlr_dvr_wr_not_rd    : STD_LOGIC;
-  SIGNAL ctlr_dvr_start_addr   : t_tech_ddr_addr;
-  SIGNAL ctlr_dvr_end_addr     : t_tech_ddr_addr;
+  SIGNAL ctlr_dvr_start_addr   : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
+  SIGNAL ctlr_dvr_end_addr     : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
   SIGNAL ctlr_dvr_wr_flush_en  : STD_LOGIC := '0';
     
   SIGNAL ctlr_init_done        : STD_LOGIC;
@@ -352,8 +353,8 @@ BEGIN
 
     dvr_en          => ctlr_dvr_en,
     dvr_wr_not_rd   => ctlr_dvr_wr_not_rd,
-    dvr_start_addr  => ctlr_dvr_start_addr,
-    dvr_end_addr    => ctlr_dvr_end_addr, 
+    dvr_start_address  => ctlr_dvr_start_addr,
+    dvr_end_address    => ctlr_dvr_end_addr, 
     dvr_done        => ctlr_dvr_done,
     
     wr_fifo_usedw   => ctlr_wr_fifo_usedw,

libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd

@@ -50,8 +50,8 @@ ENTITY io_ddr_cross_domain IS
     dvr_en                 : IN  STD_LOGIC;
     dvr_done               : OUT STD_LOGIC;
     dvr_wr_not_rd          : IN  STD_LOGIC;
-    dvr_start_addr         : IN  t_tech_ddr_addr;
-    dvr_end_addr           : IN  t_tech_ddr_addr;
+    dvr_start_addr         : IN  STD_LOGIC_VECTOR;
+    dvr_end_addr           : IN  STD_LOGIC_VECTOR;
     dvr_wr_flush_en        : IN  STD_LOGIC := '0';
     
     -- DDR controller clock domain
@@ -61,8 +61,8 @@ ENTITY io_ddr_cross_domain IS
     ctlr_dvr_en            : OUT STD_LOGIC;
     ctlr_dvr_done          : IN  STD_LOGIC;
     ctlr_dvr_wr_not_rd     : OUT STD_LOGIC;
-    ctlr_dvr_start_addr    : OUT t_tech_ddr_addr;
-    ctlr_dvr_end_addr      : OUT t_tech_ddr_addr;
+    ctlr_dvr_start_addr    : OUT STD_LOGIC_VECTOR;
+    ctlr_dvr_end_addr      : OUT STD_LOGIC_VECTOR;
     ctlr_dvr_wr_flush_en   : OUT STD_LOGIC := '0'
   );
 END io_ddr_cross_domain;

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -50,7 +50,7 @@ ENTITY tb_io_ddr IS
     g_ctlr_ref_clk_period   : TIME := 5 ns;     -- 200 MHz
     g_dvr_clk_period        : TIME := 5 ns;    -- 50 ns
     g_dp_clk_period         : TIME := 5000 ps;  -- 200 MHz
-    g_dp_data_w             : NATURAL := 32;    -- 32 for mixed width and 256 for equal width FIFO
+    g_dp_data_w             : NATURAL := 256;    -- 32 for mixed width and 256 for equal width FIFO
     g_nof_repeat            : NATURAL := 2;
     g_wr_flush_mode         : STRING := "SYN"  -- "VAL", "SOP", "SYN"
   );
@@ -62,20 +62,14 @@ ARCHITECTURE str of tb_io_ddr IS
 
   CONSTANT c_tech_ddr         : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
   
---  CONSTANT c_ddr_addr_hi      : t_tech_ddr_addr := ((OTHERS=>'0'),
---                                                    (OTHERS=>'0'),
---                                                    TO_UVEC(                                         3, c_tech_ddr_max.a_row_w),
---                                                    TO_UVEC(2**c_tech_ddr_4g.a_col_w-c_tech_ddr_4g.rsl, c_tech_ddr_max.a_col_w));
-  CONSTANT c_ddr_addr_hi      : t_tech_ddr_addr := ((OTHERS=>'0'),
-                                                    (OTHERS=>'0'),
-                                                    TO_UVEC(                                         3, c_tech_ddr_max.a_row_w),
-                                                    TO_UVEC(2**c_tech_ddr_4g.a_col_w-1, c_tech_ddr_max.a_col_w));
+  CONSTANT c_ctlr_address_w   : NATURAL := func_tech_ddr_ctlr_address_w(c_tech_ddr);
+  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
+  
   -- DDR access stimuli
-  CONSTANT c_address_lo_arr   : t_nat_natural_arr := (  0, 517,    0,     1,   2,   1,   2,   3,   5,  1900, 1900);
-  CONSTANT c_nof_address_arr  : t_nat_natural_arr := (517, 507, 1024,     1,   6,   1,   1,   2,   3,   153,  153);
-  CONSTANT c_wr_not_rd_arr    : STD_LOGIC_VECTOR  := ('1', '1',  '0',   '1', '1', '0', '0', '0', '0',    '1', '0');
+  CONSTANT c_ctlr_address_lo_arr   : t_nat_natural_arr := (  0, 517,    0,     1,   2,   1,   2,   3,   5,  1900, 1900);
+  CONSTANT c_ctlr_nof_address_arr  : t_nat_natural_arr := (517, 507, 1024,     1,   6,   1,   1,   2,   3,   153,  153);
+  CONSTANT c_ctlr_wr_not_rd_arr    : STD_LOGIC_VECTOR  := ('1', '1',  '0',   '1', '1', '0', '0', '0', '0',    '1', '0');
                                                     
-  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
   CONSTANT c_dp_factor        : NATURAL := c_ctlr_data_w/g_dp_data_w;
   
   CONSTANT c_wr_fifo_depth    : NATURAL := 128;
@@ -96,8 +90,8 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dp_clk               : STD_LOGIC := '0';
   SIGNAL dp_rst               : STD_LOGIC;
 
-  SIGNAL dvr_start_addr       : t_tech_ddr_addr; 
-  SIGNAL dvr_end_addr         : t_tech_ddr_addr;
+  SIGNAL dvr_start_addr       : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0); 
+  SIGNAL dvr_end_addr         : STD_LOGIC_VECTOR(c_ctlr_address_w-1 DOWNTO 0);
 
   SIGNAL dvr_en               : STD_LOGIC;
   SIGNAL dvr_done             : STD_LOGIC;
@@ -140,8 +134,6 @@ BEGIN
   dp_rst   <= '1', '0' AFTER 100 ns;
 
   p_stimuli : PROCESS
-    VARIABLE v_addr_lo : t_tech_ddr_addr;
-    VARIABLE v_addr_hi : t_tech_ddr_addr;
   BEGIN
     tb_end          <= '0';
     dvr_en          <= '0';
@@ -161,15 +153,12 @@ BEGIN
     proc_common_wait_some_cycles(ctlr_clk, 100);
     
     FOR R IN 0 TO g_nof_repeat-1 LOOP
-      FOR I IN c_address_lo_arr'RANGE LOOP
-        v_addr_lo := func_tech_ddr_dq_address(TO_DDR_CTLR_ADDRESS(4*c_address_lo_arr(I))                         , c_tech_ddr);
-        v_addr_hi := func_tech_ddr_dq_address(TO_DDR_CTLR_ADDRESS(4*c_address_lo_arr(I)+4*c_nof_address_arr(I)-1), c_tech_ddr);
-        
-        dvr_start_addr <= v_addr_lo;
-        dvr_end_addr   <= v_addr_hi;
-        
+      FOR I IN c_ctlr_address_lo_arr'RANGE LOOP
+        dvr_start_addr <= TO_UVEC(c_ctlr_address_lo_arr(I)                            , c_ctlr_address_w);
+        dvr_end_addr   <= TO_UVEC(c_ctlr_address_lo_arr(I)+c_ctlr_nof_address_arr(I)-1, c_ctlr_address_w);
+
         -- START ACCESS
-        dvr_wr_not_rd <= c_wr_not_rd_arr(I);
+        dvr_wr_not_rd <= c_ctlr_wr_not_rd_arr(I);
         dvr_en        <= '1';
         proc_common_wait_some_cycles(dvr_clk, 1);
         dvr_en        <= '0'; 
@@ -177,8 +166,8 @@ BEGIN
         -- ACCESS DONE
         proc_common_wait_until_lo_hi(dvr_clk, dvr_done);
         
-        IF c_wr_not_rd_arr(I)='0' THEN
-          expected_cnt <= expected_cnt + c_nof_address_arr(I)*c_dp_factor;
+        IF c_ctlr_wr_not_rd_arr(I)='0' THEN
+          expected_cnt <= expected_cnt + c_ctlr_nof_address_arr(I)*c_dp_factor;
         
           ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!"  SEVERITY FAILURE;
           ASSERT snk_diag_res = '0'     REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;