Define g_delay_len : NATURAL := c_meta_delay_len.

libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd

@@ -40,15 +40,16 @@ USE dp_lib.dp_stream_pkg.ALL;
 
 ENTITY io_ddr_cross_domain IS
   GENERIC (
-    g_cross_domain : BOOLEAN := TRUE
+    g_cross_domain : BOOLEAN := TRUE;
+    g_delay_len    : NATURAL := c_meta_delay_len
   );                      
   PORT (
     -- Driver clock domain
     dvr_clk                : IN  STD_LOGIC;
     dvr_rst                : IN  STD_LOGIC;
     
-    dvr_en                 : IN  STD_LOGIC;
     dvr_done               : OUT STD_LOGIC;
+    dvr_en                 : IN  STD_LOGIC;
     dvr_wr_not_rd          : IN  STD_LOGIC;
     dvr_start_address      : IN  STD_LOGIC_VECTOR;
     dvr_nof_data           : IN  STD_LOGIC_VECTOR;
@@ -58,8 +59,8 @@ ENTITY io_ddr_cross_domain IS
     ctlr_clk               : IN  STD_LOGIC;
     ctlr_rst               : IN  STD_LOGIC;
     
-    ctlr_dvr_en            : OUT STD_LOGIC;
     ctlr_dvr_done          : IN  STD_LOGIC;
+    ctlr_dvr_en            : OUT STD_LOGIC;
     ctlr_dvr_wr_not_rd     : OUT STD_LOGIC;
     ctlr_dvr_start_address : OUT STD_LOGIC_VECTOR;
     ctlr_dvr_nof_data      : OUT STD_LOGIC_VECTOR;
@@ -91,7 +92,7 @@ BEGIN
     -- dvr_clk --> ctlr_clk
     u_common_spulse_ctlr_dvr_en : ENTITY common_lib.common_spulse
     GENERIC MAP (
-      g_delay_len => c_meta_delay_len
+      g_delay_len => g_delay_len
     )
     PORT MAP (
       in_rst    => dvr_rst,
@@ -110,7 +111,7 @@ BEGIN
     
     u_common_spulse_ctlr_dvr_wr_flush_en : ENTITY common_lib.common_spulse
     GENERIC MAP (
-      g_delay_len => c_meta_delay_len
+      g_delay_len => g_delay_len
     )
     PORT MAP (
       in_rst    => dvr_rst,
@@ -125,7 +126,7 @@ BEGIN
     u_common_async_dvr_done : ENTITY common_lib.common_async
     GENERIC MAP (
       g_rst_level => '0',
-      g_delay_len => c_meta_delay_len
+      g_delay_len => g_delay_len
     )
     PORT MAP (
       rst  => dvr_rst,