sort file list backward to generate ddr3_mem_model before ddr3_uphy_4g_800_master (required in ddr3_mem_model/generate_ip.sh)

 to fix wrong path of 'memory_file'.

-Fixed fast accumulator model;
-Generated proper HEX files to match 48-vis rewiring stage;
-Stripped development code from top level;
-Added FIXME tags to top level with descriptions;
-Added recorded .rec files;
-Set coefficient width back to 18b;
-Set WPFB output to 9b so correlator output becomes a nice 32b;
-Verified in sim: PLOTs are slightly off!

- Switched fail and ok in reg map
- Removed comments