Commits · 32fc5d387c2fd20d95bc497a1c296bd53c15c43a · RTSD / HDL · GitLab

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Dec 03, 2019
- New IP for jesd204b interface; Unb2c test revisions; Add loopback parameter to 10GbE IP · 32fc5d38
  Jonathan Hargreaves authored 5 years ago
  
  32fc5d38
Oct 24, 2019
- changed missed library names from 170 to 180 · 963a0fff
  Pieter Donker authored 5 years ago
  
  963a0fff
Oct 21, 2019
- changes mostly in cfg and tcl files for running commandline tools · 9bcacf7a
  Pieter Donker authored 5 years ago
  
  9bcacf7a
Oct 09, 2019
- changes in config files · 81cffcb7
  Pieter Donker authored 5 years ago
  
  81cffcb7
Oct 02, 2019
- changed quartus version from 170 to 180 · 3f602842
  Pieter Donker authored 5 years ago
  
  3f602842
Aug 22, 2019
- backup last changes, build for unb2b not working · b0c776a4
  Pieter Donker authored 5 years ago
  
  b0c776a4
Jul 02, 2018
- added variations for arria10_e1sg and arria10_e3sge3 · f0d129e7
  Reinier van der Walle authored 6 years ago
  
  f0d129e7
Jun 01, 2018
- added instance for arria10_e1sg · 6b909989
  Reinier van der Walle authored 7 years ago
  
  6b909989
Dec 14, 2017
- Added dbg_g_tech_ddr. · ded52197
  Eric Kooistra authored 7 years ago
  
  ded52197
- Added func_tech_ddr_sim_size() to derive (smaller) required DDR size for... · ca735189
  Eric Kooistra authored 7 years ago
  ca735189
- Added debug signals for view in Wave window. · 88f1cb7b
  Eric Kooistra authored 7 years ago
  
  88f1cb7b
Dec 08, 2017
- Imporved g_sim_model description comment. · c8ebfe11
  Eric Kooistra authored 7 years ago
  
  c8ebfe11
Jul 25, 2017
- edited hdllib.cfg and the vhd files of several technology libraries to · dccde9ef
  Reinier van der Walle authored 7 years ago
  dccde9ef
Jun 13, 2017
- Fixed DDR simulation model. · a2f529f6
  Eric Kooistra authored 8 years ago
  
  a2f529f6
- Corrected sim_ddr model, tb_io_ddr now passes with g_sim_model = true. · 57034f10
  Eric Kooistra authored 8 years ago
  
  57034f10
Feb 15, 2017
- Modify technology wrappers to include unb2b FPGA Arria 10 version e1sg · e50aab24
  Jonathan Hargreaves authored 8 years ago
  
  e50aab24
May 17, 2016
- hdl_lib_technology = ip_arria10_e3sge3 · 30568303
  Eric Kooistra authored 9 years ago
  
  30568303
May 12, 2016
- Added regression_test_vhdl, but without tb. · 7f482f03
  Eric Kooistra authored 9 years ago
  
  7f482f03
May 11, 2016
- Added missing library declaration for ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151 · 691fe3ed
  Eric Kooistra authored 9 years ago
  
  691fe3ed
Apr 28, 2016
- Use hdl_lib_uses_ip for the multiple choice IP. · 80100686
  Eric Kooistra authored 9 years ago
  
  80100686
Apr 19, 2016
- Added [section headers]. · b232c8c7
  Eric Kooistra authored 9 years ago
  
  b232c8c7
Mar 11, 2016
- fix duplicate drivers in wrapper · 044030e0
  Jonathan Hargreaves authored 9 years ago
  
  044030e0
Mar 10, 2016
- add ddr4_8g_1600 to packages and wrappers · eecc4c7e
  Jonathan Hargreaves authored 9 years ago
  
  eecc4c7e
Jan 29, 2016
- update technology wrapper to include device e3sge3 for unb2a · 16efe183
  Jonathan Hargreaves authored 9 years ago
  
  16efe183
Oct 12, 2015
- Aligned interfaces · 1509e18f
  Zanting authored 9 years ago
  
  1509e18f
- Aligned interfaces · ffd65ec4
  Zanting authored 9 years ago
  
  ffd65ec4
Oct 01, 2015
- fixed DDR3 IP for 16GB SO-Dimms · aa76980d
  Zanting authored 9 years ago
  
  aa76980d
Sep 30, 2015
- Reverted to own pll/dll for 4g single rank slave · cde216f4
  Zanting authored 9 years ago
  
  cde216f4
- IP for 16GB DDR3 So-Dimm modules added · 878ceca5
  Zanting authored 9 years ago
  
  878ceca5
- IP for 16GB DDR3 So-Dimm modules added · 4750ad20
  Zanting authored 9 years ago
  
  4750ad20
Sep 28, 2015
- IP for 16GB DDR3 So-Dimm modules added · 67c8bcec
  Zanting authored 9 years ago
  
  67c8bcec
Sep 25, 2015
- can choose now ddr4 1600 or 2000 · fda9eccc
  Kenneth Hiemstra authored 9 years ago
  
  fda9eccc
Aug 18, 2015
- added ddr4_4g_2000 IP · 08d9a16e
  Kenneth Hiemstra authored 9 years ago
  
  08d9a16e
Aug 13, 2015
- changed c_tech_ddr4_max to use a dual rank DDR4 as single rank (see · e39ca9bd
  Kenneth Hiemstra authored 9 years ago
  e39ca9bd
- using a dual rank DDR4 but the IP is single rank: disabling 2nd rank by · 0e2b1046
  Kenneth Hiemstra authored 9 years ago
  0e2b1046
Jun 26, 2015
- Improved legenda of cs_w and cs_w_w in table. · 3f0a25a0
  Eric Kooistra authored 9 years ago
  
  3f0a25a0
Jun 24, 2015
- -Removed unused signals and constants. · 588a8417
  Daniel van der Schuur authored 9 years ago
  
  588a8417
- -Changed name of generate and instance name to match entity name to ease wave · d2af806a
  Daniel van der Schuur authored 9 years ago
  d2af806a
Jun 23, 2015
- Default mts=1600 for DDR4 sim models · bf002039
  Eric Kooistra authored 9 years ago
  
  bf002039
- Use dedicated MB ref_clk input instead of via t_tech_ddr4_phy_in. · 109f99ce
  Eric Kooistra authored 9 years ago
  
  109f99ce