backup last changes, build for unb2b not working

.gitignore

+*log
+build*
+*generated
+*pyc

boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg

 hdl_lib_name = unb1_bn_capture
 hdl_library_clause_name = unb1_bn_capture_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag aduh 
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -22,19 +23,19 @@ regression_test_vhdl =
     tb/vhdl/tb_node_unb1_bn_capture.vhd
 
 [modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/io/i2c/tb/data data   
-                      $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/io/i2c/tb/data data   
+                      $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = quartus/sopc_unb1_bn_capture.sopc .
-                     $RADIOHDL/libraries/io/i2c/tb/data data
-                     $RADIOHDL/libraries/base/diag/src/data data
+                     $RADIOHDL_WORK/libraries/io/i2c/tb/data data
+                     $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_bn_capture_pins.tcl
@@ -42,7 +43,7 @@ quartus_tcl_files =
 quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 
 

boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl

 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- BN_BI ADC pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
 
 

boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg

 hdl_lib_name = unb1_bn_terminal_bg
 hdl_library_clause_name = unb1_bn_terminal_bg_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag bf  
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =
@@ -14,17 +15,17 @@ test_bench_files =
 
 
 [modelsim_project_file]
-modelsim_copy_files = $RADIOHDL/libraries/base/diag/src/data data
+modelsim_copy_files = $RADIOHDL_WORK/libraries/base/diag/src/data data
 
 
 [quartus_project_file]
 synth_top_level_entity =
 
 quartus_copy_files = quartus/sopc_unb1_bn_terminal_bg.sopc .
-                     $RADIOHDL/libraries/base/diag/src/data data 
+                     $RADIOHDL_WORK/libraries/base/diag/src/data data 
 
 quartus_qsf_files = 
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_bn_terminal_bg_pins.tcl
@@ -32,4 +33,4 @@ quartus_tcl_files =
 quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc

boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl

 # Pin assignments
 # -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
 # -- 1GbE Control Interface
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
 # -- I2C Interface to Sensors
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 # -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
 # -- Mesh pins. 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
 
 

boards/uniboard1/designs/unb1_ddr3/doc/README

@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3] in RadionHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3

boards/uniboard1/designs/unb1_ddr3/hdllib.cfg

@@ -16,7 +16,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
     quartus/sopc_unb1_ddr3.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
@@ -36,5 +36,5 @@ quartus_tcl_files =
     quartus/unb1_ddr3_pins_constraints.tcl
     
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
     

boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl

@@ -20,8 +20,8 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-#source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl

boards/uniboard1/designs/unb1_ddr3_reorder/doc/README

@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3_reorder] in RadioHDL
 --------------------------------------------------------------
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC:
     run_sopc unb1 unb1_ddr3_reorder

boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl

@@ -20,7 +20,7 @@
 ###############################################################################
 
 # -- include ddr3 pins
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 
 # -- include the clock pin
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg

@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
-    $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
     

boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg

@@ -22,7 +22,7 @@ modelsim_copy_files =
     ../../src/hex hex
 
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
     
 
 [quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
     ../../src/hex hex
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     ../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,6 +42,6 @@ quartus_tcl_files =
 quartus_vhdl_files = 
 
 quartus_qip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
-    $RADIOHDL/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/generated/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+    $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
     

boards/uniboard1/designs/unb1_ddr3_transpose/doc/README

@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_ddr3_transpose] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_ddr3_transpose

boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg

@@ -16,7 +16,7 @@ test_bench_files =
 
 [modelsim_project_file]
 modelsim_compile_ip_files =
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
 
 
 [quartus_project_file]
@@ -26,7 +26,7 @@ quartus_copy_files =
     quartus/sopc_unb_ddr3_transpose.sopc .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
     
 quartus_tcl_files =
     quartus/unb1_ddr3_transpose_pins.tcl
@@ -36,5 +36,5 @@ quartus_vhdl_files =
 
 quartus_qip_files =
     $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
-    $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+    $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
 

boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl

@@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
 source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
 

boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg

 hdl_lib_name = unb1_fn_terminal_db
 hdl_library_clause_name = unb1_fn_terminal_db_lib
 hdl_lib_uses_synth = common technology mm i2c unb1_board diag 
+hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 
 synth_files =   
@@ -22,7 +23,7 @@ synth_top_level_entity =
 quartus_copy_files = quartus/sopc_unb1_fn_terminal_db.sopc .
 
 quartus_qsf_files =                                                       
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_tcl_files =
     quartus/unb1_fn_terminal_db_pins.tcl

boards/uniboard1/designs/unb1_heater/doc/README

@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_heater] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_qsys unb1 unb1_heater

boards/uniboard1/designs/unb1_heater/hdllib.cfg

@@ -23,10 +23,10 @@ quartus_copy_files =
     quartus/qsys_unb1_heater.qsys .
 
 quartus_qsf_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
 
 quartus_sdc_files =
-    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+    $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
 
 quartus_tcl_files =
     quartus/unb1_heater_pins.tcl

boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl

@@ -19,8 +19,8 @@
 #
 ###############################################################################
 
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
 

boards/uniboard1/designs/unb1_minimal/doc/README

@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_minimal] in RadionHDL
 
 
 Start with the Oneclick Commands:
-    python $RADIOHDL/tools/oneclick/base/modelsim_config.py
-    python $RADIOHDL/tools/oneclick/base/quartus_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
+    python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
 
 Generate MMM for SOPC and QSYS:
     run_sopc unb1 unb1_minimal_sopc
@@ -58,12 +58,12 @@ Convert .sof to .rbf:
 
 
 Send to LCU capture5:
-    scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
+    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/  # QSYS
     or:
-    scp $RADIOHDL/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
+    scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/  # SOPC
 
     # Now login on capture5 and use pythonscript to program flash:
-    cd $RADIOHDL/boards/uniboard1/designs/unb1_minimal/tb/python
+    cd $RADIOHDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
 
     # for example use frontnode 0 on uniboard 0:
     python tc_unb1_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb1_minimal_qsys.rbf   # QSYS