added ddr4_4g_2000 IP

libraries/technology/ddr/hdllib.cfg

@@ -5,6 +5,7 @@ hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
                      ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
                      ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave
                      ip_arria10_ddr4_4g_1600
+                     ip_arria10_ddr4_4g_2000
                      ip_arria10_ddr4_8g_2400
                      common
 hdl_lib_uses_sim = ip_stratixiv_ddr3_mem_model

libraries/technology/ddr/tech_ddr_arria10.vhd

@@ -34,7 +34,8 @@
 --   DDR interface monitoring purposes.
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_ddr4_4g_1600_altera_emif_150;
+--LIBRARY ip_arria10_ddr4_4g_1600_altera_emif_150;
+LIBRARY ip_arria10_ddr4_4g_2000_altera_emif_150;
 
 LIBRARY IEEE, technology_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -89,13 +90,14 @@ BEGIN
   ref_rst_n    <= NOT ref_rst;
   ctlr_gen_rst <= NOT ctlr_gen_rst_n;
     
-  gen_ip_arria10_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
+  --gen_ip_arria10_ddr4_4g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
+  gen_ip_arria10_ddr4_4g_2000 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=4 AND g_tech_ddr.mts=1600 GENERATE
 
     phy_ou.cs_n(1) <= '1';
     phy_ou.cke(1)  <= '0';
     phy_ou.odt(1)  <= '0';
 
-    u_ip_arria10_ddr4_4g_1600 : ip_arria10_ddr4_4g_1600
+    u_ip_arria10_ddr4_4g_2000 : ip_arria10_ddr4_4g_2000
     PORT MAP (
       amm_ready_0         => ctlr_miso.waitrequest_n,                                   --     ctrl_amm_avalon_slave_0.waitrequest_n
       amm_read_0          => ctlr_mosi.rd,                                              --                            .read

libraries/technology/ddr/tech_ddr_component_pkg.vhd

@@ -278,6 +278,44 @@ PACKAGE tech_ddr_component_pkg IS
     local_cal_fail      : out   std_logic                                          --                            .local_cal_fail
   );
   END COMPONENT;
+
+  -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/generated/sim/ip_arria10_ddr4_4g_2000.vhd
+  COMPONENT ip_arria10_ddr4_4g_2000 IS
+  PORT (
+    amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
+    amm_read_0          : in    std_logic                      := '0';             --                            .read
+    amm_write_0         : in    std_logic                      := '0';             --                            .write
+    amm_address_0       : in    std_logic_vector(25 downto 0)  := (others => '0'); --                            .address
+    amm_readdata_0      : out   std_logic_vector(575 downto 0);                    --                            .readdata
+    amm_writedata_0     : in    std_logic_vector(575 downto 0) := (others => '0'); --                            .writedata
+    amm_burstcount_0    : in    std_logic_vector(6 downto 0)   := (others => '0'); --                            .burstcount
+    amm_byteenable_0    : in    std_logic_vector(71 downto 0)  := (others => '0'); --                            .byteenable
+    amm_readdatavalid_0 : out   std_logic;                                         --                            .readdatavalid
+    emif_usr_clk        : out   std_logic;                                         --   emif_usr_clk_clock_source.clk
+    emif_usr_reset_n    : out   std_logic;                                         -- emif_usr_reset_reset_source.reset_n
+    global_reset_n      : in    std_logic                      := '0';             --     global_reset_reset_sink.reset_n
+    mem_ck              : out   std_logic_vector(0 downto 0);                      --             mem_conduit_end.mem_ck
+    mem_ck_n            : out   std_logic_vector(0 downto 0);                      --                            .mem_ck_n
+    mem_a               : out   std_logic_vector(16 downto 0);                     --                            .mem_a
+    mem_act_n           : out   std_logic_vector(0 downto 0);                      --                            .mem_act_n
+    mem_ba              : out   std_logic_vector(1 downto 0);                      --                            .mem_ba
+    mem_bg              : out   std_logic_vector(1 downto 0);                      --                            .mem_bg
+    mem_cke             : out   std_logic_vector(0 downto 0);                      --                            .mem_cke
+    mem_cs_n            : out   std_logic_vector(0 downto 0);                      --                            .mem_cs_n
+    mem_odt             : out   std_logic_vector(0 downto 0);                      --                            .mem_odt
+    mem_reset_n         : out   std_logic_vector(0 downto 0);                      --                            .mem_reset_n
+    mem_par             : out   std_logic_vector(0 downto 0);                      --                            .mem_par
+    mem_alert_n         : in    std_logic_vector(0 downto 0)   := (others => '0'); --                            .mem_alert_n
+    mem_dqs             : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs
+    mem_dqs_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs_n
+    mem_dq              : inout std_logic_vector(71 downto 0)  := (others => '0'); --                            .mem_dq
+    mem_dbi_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dbi_n
+    oct_rzqin           : in    std_logic                      := '0';             --             oct_conduit_end.oct_rzqin
+    pll_ref_clk         : in    std_logic                      := '0';             --      pll_ref_clk_clock_sink.clk
+    local_cal_success   : out   std_logic;                                         --          status_conduit_end.local_cal_success
+    local_cal_fail      : out   std_logic                                          --                            .local_cal_fail
+  );
+  END COMPONENT;
   
 END tech_ddr_component_pkg;
 

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -91,6 +91,7 @@ PACKAGE tech_ddr_pkg IS
   CONSTANT c_tech_ddr4_sim_1m                     : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 10,  9, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
   
   CONSTANT c_tech_ddr4_4g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
+  CONSTANT c_tech_ddr4_4g_2000m                   : t_c_tech_ddr := ("DDR4", 2000,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
 
   -- PHY in, inout and out signal records
   TYPE t_tech_ddr3_phy_in IS RECORD                                                                 -- DDR3 Description