Fixed DDR simulation model.
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- libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd 1 addition, 1 deletionlibraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
- libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd 3 additions, 6 deletionslibraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
- libraries/technology/ddr/sim_ddr.vhd 112 additions, 97 deletionslibraries/technology/ddr/sim_ddr.vhd
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