changed missed library names from 170 to 180

hdl_user_components.ipx

@@ -7,5 +7,4 @@
  <!--  -->
  <!-- D:/svnroot/Uniboard/9.0 -->
  <path path="$RADIOHDL_WORK/libraries/**/*" />
- <path path="$HDL_BUILD_DIR/**/*" />
 </library>

init_hdl.sh

@@ -47,7 +47,7 @@ echo "HDL environment will be setup for" $RADIOHDL_WORK
 user_components_file="${ALTERA_DIR}/user_components.ipx"
 if [ -e $user_components_file ]; then
   echo "removing existing user_components.ipx symbolic link"
-  rm $user_components_file
+  rm -f $user_components_file
 fi
 # make a new symbolic link to the git version
 echo "making a new symbolic link"

libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd

@@ -21,18 +21,18 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_180;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_180;
 
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/clkbuf/tech_clkbuf.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
 LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_180;
 
 ENTITY tech_clkbuf IS
   GENERIC (

libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd

@@ -34,10 +34,10 @@
 --   DDR interface monitoring purposes.
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180;
 
 LIBRARY IEEE, technology_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/flash/tech_flash_asmi_parallel.vhd

@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
 LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
---LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
+--LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_180;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (

libraries/technology/flash/tech_flash_remote_update.vhd

@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_remote_update_altera_remote_update_150;
 LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_180;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
 LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
 
 
 ENTITY tech_fpga_temp_sens IS

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
 LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
 
 
 ENTITY tech_fpga_voltage_sens IS

libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_fractional_pll_clk125 IS
   GENERIC (

libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_fractional_pll_clk200 IS
   GENERIC (

libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd

@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_180;
 
 LIBRARY IEEE, technology_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/mult/tech_complex_mult.vhd

@@ -31,7 +31,7 @@ LIBRARY ip_stratixiv_mult_lib;
 --LIBRARY ip_arria10_mult_lib;
 --LIBRARY ip_arria10_mult_rtl_lib;
 LIBRARY ip_arria10_complex_mult_altmult_complex_150;
-LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
+LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_180;
 LIBRARY ip_arria10_complex_mult_rtl_lib;
 LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
 

libraries/technology/pll/tech_pll_clk125.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_180;
 
 ENTITY tech_pll_clk125 IS
   GENERIC (

libraries/technology/pll/tech_pll_clk200.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_pll_lib;
 LIBRARY ip_arria10_pll_clk200_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk200_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk200_altera_iopll_180;
 
 ENTITY tech_pll_clk200 IS
   GENERIC (

libraries/technology/pll/tech_pll_clk25.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_arria10_pll_clk25_altera_iopll_150;
 LIBRARY ip_stratixiv_pll_clk25_lib;
 LIBRARY ip_arria10_e3sge3_pll_clk25_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_170;
+LIBRARY ip_arria10_e1sg_pll_clk25_altera_iopll_180;
 
 ENTITY tech_pll_clk25 IS
   GENERIC (

libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd

@@ -43,7 +43,7 @@ USE common_lib.common_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170;
+LIBRARY ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_180;
 
 ENTITY tech_pll_xgmii_mac_clocks IS
   GENERIC (

libraries/technology/tse/tech_tse_arria10_e1sg.vhd

@@ -28,8 +28,8 @@ USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_170;
-LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_170;
+LIBRARY ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180;
+LIBRARY ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180;
 
 ENTITY tech_tse_arria10_e1sg IS
   GENERIC (