Added regression_test_vhdl, but without tb.

libraries/technology/clkbuf/hdllib.cfg

@@ -11,6 +11,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/ddr/hdllib.cfg

@@ -30,6 +30,9 @@ test_bench_files =
     tech_ddr_mem_model_component_pkg.vhd
     tech_ddr_mem_model.vhd
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/fifo/hdllib.cfg

@@ -12,6 +12,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/flash/hdllib.cfg

@@ -16,6 +16,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/fpga_temp_sens/hdllib.cfg

@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/fpga_voltage_sens/hdllib.cfg

@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/fractional_pll/hdllib.cfg

@@ -13,6 +13,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/hdllib.cfg

@@ -10,6 +10,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/iobuf/hdllib.cfg

@@ -11,6 +11,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/memory/hdllib.cfg

@@ -14,6 +14,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/mult/hdllib.cfg

@@ -19,6 +19,9 @@ synth_files =
 
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]
 

libraries/technology/pll/hdllib.cfg

@@ -18,6 +18,9 @@ synth_files =
     
 test_bench_files =
 
+regression_test_vhdl = 
+    # no self checking tb available yet
+
 
 [modelsim_project_file]