edited hdllib.cfg and the vhd files of several technology libraries to

use the correct library names in the .../technology/ip_arria10_e1sg
folder

libraries/technology/10gbase_r/hdllib.cfg

@@ -38,15 +38,15 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_transceiver_reset_controller_24  ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
     ip_arria10_e3sge3_transceiver_reset_controller_48  ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
     ip_arria10_e1sg_phy_10gbase_r                      ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
-    ip_arria10_e1sg_phy_10gbase_r_4                    ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
-    ip_arria10_e1sg_phy_10gbase_r_12                   ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
-    ip_arria10_e1sg_phy_10gbase_r_24                   ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
-    ip_arria10_e1sg_phy_10gbase_r_48                   ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
-    ip_arria10_e1sg_transceiver_pll_10g                ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
-    ip_arria10_e1sg_transceiver_reset_controller_1     ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
-    ip_arria10_e1sg_transceiver_reset_controller_4     ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
-    ip_arria10_e1sg_transceiver_reset_controller_12    ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
-    ip_arria10_e1sg_transceiver_reset_controller_24    ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+    ip_arria10_e1sg_phy_10gbase_r_4                    ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
+    ip_arria10_e1sg_phy_10gbase_r_12                   ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
+    ip_arria10_e1sg_phy_10gbase_r_24                   ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
+    ip_arria10_e1sg_phy_10gbase_r_48                   ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
+    ip_arria10_e1sg_transceiver_pll_10g                ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
+    ip_arria10_e1sg_transceiver_reset_controller_1     ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
+    ip_arria10_e1sg_transceiver_reset_controller_4     ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
+    ip_arria10_e1sg_transceiver_reset_controller_12    ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
+    ip_arria10_e1sg_transceiver_reset_controller_24    ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
 
 synth_files =
     sim_10gbase_r.vhd

libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd

@@ -21,17 +21,17 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151;
-LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170;
+LIBRARY ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_170;
 
 LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/clkbuf/hdllib.cfg

@@ -7,7 +7,7 @@ hdl_lib_technology =
 hdl_lib_disclose_library_clause_names =
     ip_arria10_clkbuf_global         ip_arria10_clkbuf_global_altclkctrl_150
     ip_arria10_e3sge3_clkbuf_global  ip_arria10_e3sge3_clkbuf_global_altclkctrl_151
-    ip_arria10_e1sg_clkbuf_global    ip_arria10_e1sg_clkbuf_global_altclkctrl_151
+    ip_arria10_e1sg_clkbuf_global    ip_arria10_e1sg_clkbuf_global_altclkctrl_170
 
 synth_files =
     tech_clkbuf_component_pkg.vhd

libraries/technology/clkbuf/tech_clkbuf.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
 LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
-LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_151;
+LIBRARY ip_arria10_e1sg_clkbuf_global_altclkctrl_170;
 
 ENTITY tech_clkbuf IS
   GENERIC (

libraries/technology/ddr/hdllib.cfg

@@ -33,10 +33,10 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_ddr4_8g_1600                   ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151
     ip_arria10_e3sge3_ddr4_4g_2000                   ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151
     ip_arria10_e3sge3_ddr4_8g_2400                   ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
-    ip_arria10_e1sg_ddr4_4g_1600                     ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
-    ip_arria10_e1sg_ddr4_8g_1600                     ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
-    ip_arria10_e1sg_ddr4_4g_2000                     ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
-    ip_arria10_e1sg_ddr4_8g_2400                     ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
+    ip_arria10_e1sg_ddr4_4g_1600                     ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170
+    ip_arria10_e1sg_ddr4_8g_1600                     ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170
+    ip_arria10_e1sg_ddr4_4g_2000                     ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170
+    ip_arria10_e1sg_ddr4_8g_2400                     ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170
     ip_stratixiv_ddr3_mem_model                      ip_stratixiv_ddr3_mem_model_lib
     ip_arria10_ddr4_mem_model_141                    ip_arria10_ddr4_mem_model_141
     

libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd

@@ -34,10 +34,10 @@
 --   DDR interface monitoring purposes.
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151;
-LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151;
+LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_170;
+LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_170;
 
 LIBRARY IEEE, technology_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/flash/hdllib.cfg

@@ -16,8 +16,8 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_remote_update        ip_arria10_remote_update_altera_remote_update_150
     ip_arria10_e3sge3_asmi_parallel ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151
     ip_arria10_e3sge3_remote_update ip_arria10_e3sge3_remote_update_altera_remote_update_151
-    ip_arria10_e1sg_asmi_parallel   ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
-    ip_arria10_e1sg_remote_update   ip_arria10_e1sg_remote_update_altera_remote_update_151
+    ip_arria10_e1sg_asmi_parallel   ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170
+    ip_arria10_e1sg_remote_update   ip_arria10_e1sg_remote_update_altera_remote_update_170
     
 synth_files =
     tech_flash_component_pkg.vhd

libraries/technology/flash/tech_flash_asmi_parallel.vhd

@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
 LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
-LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151;
+LIBRARY ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_170;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (

libraries/technology/flash/tech_flash_remote_update.vhd

@@ -31,7 +31,7 @@ USE technology_lib.technology_select_pkg.ALL;
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_remote_update_altera_remote_update_150;
 LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
-LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_151;
+LIBRARY ip_arria10_e1sg_remote_update_altera_remote_update_170;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (

libraries/technology/fpga_temp_sens/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology =
 hdl_lib_disclose_library_clause_names =
     ip_arria10_temp_sense        ip_arria10_temp_sense_altera_temp_sense_150
     ip_arria10_e3sge3_temp_sense ip_arria10_e3sge3_temp_sense_altera_temp_sense_151
-    ip_arria10_e1sg_temp_sense   ip_arria10_e1sg_temp_sense_altera_temp_sense_151
+    ip_arria10_e1sg_temp_sense   ip_arria10_e1sg_temp_sense_altera_temp_sense_170
 
 synth_files =
     tech_fpga_temp_sens_component_pkg.vhd

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd

@@ -29,7 +29,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
 LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
-LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_151;
+LIBRARY ip_arria10_e1sg_temp_sense_altera_temp_sense_170;
 
 
 ENTITY tech_fpga_temp_sens IS

libraries/technology/fpga_voltage_sens/hdllib.cfg

@@ -6,7 +6,7 @@ hdl_lib_technology =
 hdl_lib_disclose_library_clause_names =            
     ip_arria10_voltage_sense         ip_arria10_voltage_sense_altera_voltage_sense_150
     ip_arria10_e3sge3_voltage_sense  ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151
-    ip_arria10_e1sg_voltage_sense    ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
+    ip_arria10_e1sg_voltage_sense    ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170
 
 synth_files =
     tech_fpga_voltage_sens_component_pkg.vhd

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
 LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
-LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151;
+LIBRARY ip_arria10_e1sg_voltage_sense_altera_voltage_sense_170;
 
 
 ENTITY tech_fpga_voltage_sens IS

libraries/technology/fractional_pll/hdllib.cfg

@@ -10,8 +10,8 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_fractional_pll_clk125         ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150
     ip_arria10_e3sge3_fractional_pll_clk200  ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151
     ip_arria10_e3sge3_fractional_pll_clk125  ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151
-    ip_arria10_e1sg_fractional_pll_clk200    ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
-    ip_arria10_e1sg_fractional_pll_clk125    ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+    ip_arria10_e1sg_fractional_pll_clk200    ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170
+    ip_arria10_e1sg_fractional_pll_clk125    ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170
     
 synth_files =
     tech_fractional_pll_component_pkg.vhd

libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_170;
 
 ENTITY tech_fractional_pll_clk125 IS
   GENERIC (

libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
 LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
-LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
+LIBRARY ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_170;
 
 ENTITY tech_fractional_pll_clk200 IS
   GENERIC (

libraries/technology/mac_10g/hdllib.cfg

@@ -8,7 +8,7 @@ hdl_lib_disclose_library_clause_names =
     ip_stratixiv_mac_10g      ip_stratixiv_mac_10g_lib
     ip_arria10_mac_10g        ip_arria10_mac_10g_alt_em10g32_150
     ip_arria10_e3sge3_mac_10g ip_arria10_e3sge3_mac_10g_alt_em10g32_151
-    ip_arria10_e1sg_mac_10g   ip_arria10_e1sg_mac_10g_alt_em10g32_151
+    ip_arria10_e1sg_mac_10g   ip_arria10_e1sg_mac_10g_alt_em10g32_170
 
 synth_files =
     tech_mac_10g_component_pkg.vhd

libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd

@@ -21,7 +21,7 @@
 --------------------------------------------------------------------------------
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
-LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_151;
+LIBRARY ip_arria10_e1sg_mac_10g_alt_em10g32_170;
 
 LIBRARY IEEE, technology_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;

libraries/technology/pll/hdllib.cfg

@@ -18,10 +18,10 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_pll_clk25            ip_arria10_e3sge3_pll_clk25_altera_iopll_151           
     ip_arria10_e3sge3_pll_clk125           ip_arria10_e3sge3_pll_clk125_altera_iopll_151          
     ip_arria10_e3sge3_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
-    ip_arria10_e1sg_pll_clk200             ip_arria10_e1sg_pll_clk200_altera_iopll_151          
-    ip_arria10_e1sg_pll_clk25              ip_arria10_e1sg_pll_clk25_altera_iopll_151           
-    ip_arria10_e1sg_pll_clk125             ip_arria10_e1sg_pll_clk125_altera_iopll_151          
-    ip_arria10_e1sg_pll_xgmii_mac_clocks   ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+    ip_arria10_e1sg_pll_clk200             ip_arria10_e1sg_pll_clk200_altera_iopll_170          
+    ip_arria10_e1sg_pll_clk25              ip_arria10_e1sg_pll_clk25_altera_iopll_170           
+    ip_arria10_e1sg_pll_clk125             ip_arria10_e1sg_pll_clk125_altera_iopll_170          
+    ip_arria10_e1sg_pll_xgmii_mac_clocks   ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_170
 
 synth_files =
     tech_pll_component_pkg.vhd

libraries/technology/pll/tech_pll_clk125.vhd

@@ -28,7 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_pll_clk125_altera_iopll_150;
 LIBRARY ip_arria10_e3sge3_pll_clk125_altera_iopll_151;
-LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_151;
+LIBRARY ip_arria10_e1sg_pll_clk125_altera_iopll_170;
 
 ENTITY tech_pll_clk125 IS
   GENERIC (