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HDL
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RTSD
HDL
Commits
88f1cb7b
Commit
88f1cb7b
authored
7 years ago
by
Eric Kooistra
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Added debug signals for view in Wave window.
parent
3f67173d
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libraries/technology/ddr/sim_ddr.vhd
+8
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8 additions, 2 deletions
libraries/technology/ddr/sim_ddr.vhd
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libraries/technology/ddr/sim_ddr.vhd
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View file @
88f1cb7b
...
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@@ -117,10 +117,16 @@ ARCHITECTURE str OF sim_ddr IS
SIGNAL
sim_clk
:
STD_LOGIC
;
SIGNAL
sim_rst
:
STD_LOGIC
;
SIGNAL
mem_state
:
t_mem_state
;
-- Debug signals for view in Wave window
SIGNAL
dbg_c_nof_addr
:
NATURAL
;
SIGNAL
dbg_c_dat_w
:
NATURAL
;
SIGNAL
mem_state
:
t_mem_state
;
BEGIN
dbg_c_nof_addr
<=
c_nof_addr
;
dbg_c_dat_w
<=
c_dat_w
;
-- Prevent delta delay issues by using a re-assigned clk both internally (sim_clk) and externally (ctrl_gen_clk)
ctlr_gen_clk
<=
ref_clk
;
ctlr_gen_rst
<=
ref_rst
;
...
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