Use dedicated MB ref_clk input instead of via t_tech_ddr4_phy_in.

boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl

@@ -62,8 +62,7 @@ set_location_assignment PIN_AR17 -to MB_I_OU.odt[1]     ;# size odt 1 or 2?
 set_location_assignment PIN_BC18 -to MB_I_OU.par
 set_location_assignment PIN_BB15 -to MB_I_OU.a[16]      ;# was: MB_I_RAS_A16
 
-#set_location_assignment PIN_AW17 -to MB_I_REF_CLK
-set_location_assignment PIN_AW17 -to MB_I_IN.ref_clk
+set_location_assignment PIN_AW17 -to MB_I_REF_CLK
 
 set_location_assignment PIN_AV19 -to MB_I_OU.reset_n
 set_location_assignment PIN_AY17 -to MB_I_IN.oct_rzqin  ;# was: MB_I_RZQ  (correct?)
@@ -134,8 +133,7 @@ set_location_assignment PIN_R27 -to MB_II_OU.odt[1]
 set_location_assignment PIN_R28 -to MB_II_OU.par
 set_location_assignment PIN_G28 -to MB_II_OU.a[16]      ;# was: MB_II_RAS_A16
 
-#set_location_assignment PIN_J29 -to MB_II_REF_CLK
-set_location_assignment PIN_J29 -to MB_II_IN.ref_clk
+set_location_assignment PIN_J29 -to MB_II_REF_CLK
 
 set_location_assignment PIN_L28 -to MB_II_OU.reset_n
 # RZQ changed after Altera review

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -102,7 +102,6 @@ PACKAGE tech_ddr_pkg IS
     --evt                      : STD_LOGIC;                                                         -- event signal
     alert_n                    : STD_LOGIC;                                                         -- alert signal
     oct_rzqin                  : STD_LOGIC;                                                         -- PHY has On Chip Termination OCT inputs
-    ref_clk                    : STD_LOGIC;                                                         -- reference clock input
   END RECORD;
 
   TYPE t_tech_ddr3_phy_io IS RECORD                                                                 -- DDR3 Description
@@ -166,7 +165,7 @@ PACKAGE tech_ddr_pkg IS
   CONSTANT c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((OTHERS=>'0'), (OTHERS=>'0'));
 
   CONSTANT c_tech_ddr3_phy_in_x     : t_tech_ddr3_phy_in := ('X', 'X', 'X');
-  CONSTANT c_tech_ddr4_phy_in_x     : t_tech_ddr4_phy_in := ('X', 'X', 'X');
+  CONSTANT c_tech_ddr4_phy_in_x     : t_tech_ddr4_phy_in := ('X', 'X');
   CONSTANT c_tech_ddr3_phy_ou_x     : t_tech_ddr3_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));
   CONSTANT c_tech_ddr4_phy_ou_x     : t_tech_ddr4_phy_ou := ((OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), 'X', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'), (OTHERS=>'X'));