fix duplicate drivers in wrapper

libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd

@@ -74,7 +74,7 @@ ARCHITECTURE str OF tech_ddr_arria10_e3sge3 IS
 
   CONSTANT c_gigabytes             : NATURAL := func_tech_ddr_module_size(g_tech_ddr);
 
-  CONSTANT c_ctlr_address_w        : NATURAL := 26; --func_tech_ddr_ctlr_address_w(g_tech_ddr);
+  CONSTANT c_ctlr_address_w        : NATURAL := func_tech_ddr_ctlr_address_w(g_tech_ddr);
   CONSTANT c_ctlr_data_w           : NATURAL := 576;--func_tech_ddr_ctlr_data_w(   g_tech_ddr);
   
   SIGNAL i_ctlr_gen_clk            : STD_LOGIC;
@@ -207,10 +207,6 @@ BEGIN
   
   gen_ip_arria10_e3sge3_ddr4_8g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=1600 GENERATE
 
-    phy_ou.cs_n(1) <= '1';
-    phy_ou.cke(1)  <= '0';
-    phy_ou.odt(1)  <= '0';
-
     u_ip_arria10_e3sge3_ddr4_8g_1600 : ip_arria10_e3sge3_ddr4_8g_1600
     PORT MAP (
       amm_ready_0         => ctlr_miso.waitrequest_n,                                   --     ctrl_amm_avalon_slave_0.waitrequest_n

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -92,7 +92,7 @@ PACKAGE tech_ddr_pkg IS
   CONSTANT c_tech_ddr4_sim_1m                     : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 10,  9, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
   
   CONSTANT c_tech_ddr4_4g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
-  CONSTANT c_tech_ddr4_8g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 0,   2,   0,  8,  3,    8,  64,   7);
+  CONSTANT c_tech_ddr4_8g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 1,   2,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_4g_2000m                   : t_c_tech_ddr := ("DDR4", 2000,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
 
   -- PHY in, inout and out signal records