Use hdl_lib_include and unb*_board to include the 25M and 200M PLL IP for unb1 and the 125M and 200M PLL IP for unb2, unb2a

Updated all IP related files to match Quartus 15.0 which uses libraries with _150 in their names instead of -141.

is mm_clk, tse_clk, epcs_clk, cal_reconf_clk

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

to quartus compile

Added technology independent interface for Stratix IV PLL with 200MHz clock that are used in UniBoard1 designs.