add _e3sge3 option (for unb2a) to technology wrapper

libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd

@@ -79,6 +79,18 @@ BEGIN
     );
   END GENERATE;
   
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_pll_xgmii_mac_clocks
+    PORT MAP (
+      pll_refclk0   => refclk_644,
+      pll_powerdown => rst_in,
+      pll_locked    => pll_locked,
+      outclk0       => i_clk_156,
+      pll_cal_busy  => OPEN,
+      outclk1       => i_clk_312
+    );
+  END GENERATE;
+  
   pll_locked_n <= NOT pll_locked;
   
   -- The delta-cycle difference in simulation between i_clk and output clk is no issue because i_clk is only used to create rst which is not clk cycle critical