Eric Kooistra
authored
Added technology independent interface for Stratix IV PLL with 200MHz clock that are used in UniBoard1 designs.
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| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| hdllib.cfg | ||
| tech_pll_clk200.vhd | ||
| tech_pll_clk200_p6.vhd | ||
| tech_pll_component_pkg.vhd | ||