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Created with Raphaël 2.2.020Apr19181413121110764331Mar302928272524232221201716151413108632128Feb272423222117161514139876432126Jan252419181712114223Dec2221201916158752130Nov2928252422211817161413987432131Oct28272625242120191817Also support g_dont_flip_channels for gen_two_real.Added description of g_dont_flip_channelsCorrected src_in default is c_dp_siso_rdy.Removed synthesis keys from this base design. Synthesis is done with the reveisions.Added use of dp_throttle_xon. Many more improvements.Removed unused ID port on node_apertif_unb1_correlator_processing instance.Cosmetic corrections to generic dependency of c_nof_deinterleaved_streams and g_data_w of u_dp_fifo_sc_bsnRemoved unused g_accu_nof_samples.Investigate using input clipping or wrapping for the correlator input.Commit of rbf files that were created by Hajee on or before 26th of January 2017.Added images directory for rbf files-Added command block for fiber delay compensation.read memory map after loading image-daniel in a hurry-Commented out auto-PAC-reset part.-Fixed path. For real this time.-Fixed path.-Added peripheral to set 1GbE headers.Added rule to compile VHDL file only in one library. Explained tb/vhdl and src/vhdl sub directories.Added description of quit -sim and quit -f to section 6c.Cosmetic detail.Improved by adjusting c_nof_block_on := g_nof_block_on-1. Added verify g_block_size=1,2,3 in tb_tb.Improved section 6b) on simulation and 7 on synthesis.Clarified use of 'mk' in section 6b) Compilation and makefiles.Added overload function common_math_create_look_up_table_cos/sin with amplitude, frequency and phase parameters.Renamed dp_block_gen_arr.vhd into more appropriate dp_block_gen_valid_arr.vhd.Renamed dp_block_gen_arr.vhd into more appropriate dp_block_gen_valid_arr.vhd.Only default assign snk_in.bsn/channel to src_out when g_preserve_bsn/channel=TRUE, to avoid unnecessary toggling.Added snk_out, fixed support for g_nof_data=2.Only cosmetic changes. Improved description and comments.-Added author.-Corrected wrong BG output block size / duty cycle.-Forwarding XON.-Increased witdh of gap setting (and others) to 24 bits as 16 bits is not -Added a comment linte.-Added fiber delay compensation:-Added fringe_stop to hdllib.cfg.-Fixed register name.-Defaulted monitor inputs to 0.-Added dp_xonoff_iab_i register.